[skip ci] Implement synthesis domains in primitive definitions

clash-lib/prims/common/Clash_Explicit_Signal.json

@@ -4,11 +4,13 @@
     , "kind"      : "Expression"
     , "type" :
 "unsafeSynchronizer
-  :: Clock dom1 g1
-  -> Clock dom2 g2
-  -> Signal dom1 a -- ARG[2]
+  :: ( KnownDomain dom1 conf1    -- ARG[0]
+     , KnownDomain dom2 conf2 )  -- ARG[1]
+  => Clock dom1                  -- ARG[2]
+  -> Clock dom2                  -- ARG[3]
+  -> Signal dom1 a               -- ARG[4]
   -> Signal dom2 a"
-    , "template"  : "~ARG[2]"
+    , "template"  : "~ARG[4]"
     }
   }
 ]

clash-lib/prims/commonverilog/Clash_Intel_DDR.json

@@ -4,14 +4,15 @@
     , "type" :
 "altddioOut#
   :: ( HasCallStack             -- ARG[0]
-     , fast ~ Dom n pFast       -- ARG[1]
-     , slow ~ Dom n (2*pFast)   -- ARG[2]
+     , KnownDomain fast domf    -- ARG[1]
+     , KnownDomain slow doms    -- ARG[2]
      , KnownNat m )             -- ARG[3]
   => SSymbol deviceFamily       -- ARG[4]
-  -> Clock slow gated           -- ARG[5]
-  -> Reset slow synchronous     -- ARG[6]
-  -> Signal slow (BitVector m)  -- ARG[7]
+  -> Clock slow                 -- ARG[5]
+  -> Reset slow                 -- ARG[6]
+  -> Enable slow                -- ARG[7]
   -> Signal slow (BitVector m)  -- ARG[8]
+  -> Signal slow (BitVector m)  -- ARG[9]
   -> Signal fast (BitVector m)"
     , "libraries" : ["altera_mf"]
     , "template" :
@@ -27,17 +28,15 @@ altddio_out
     .power_up_high (\"OFF\"),
     .width (~SIZE[~TYPO])
   )
-  ~GENSYM[~COMPNAME_ALTDDIO_OUT][7] (~IF ~ISSYNC[6] ~THEN
+  ~GENSYM[~COMPNAME_ALTDDIO_OUT][7] (~IF ~ISSYNC[2] ~THEN
     .sclr (~ARG[6]),
     .aclr (1'b0),~ELSE
     .aclr (~ARG[6]),
     .sclr (1'b0),~FI
-    .datain_h (~ARG[7]),
-    .datain_l (~ARG[8]),~IF ~ISGATED[5] ~THEN
-    .outclock (~ARG[5][1]),
-    .outclocken (~ARG[5][0]),~ELSE
+    .datain_h (~ARG[8]),
+    .datain_l (~ARG[9]),
     .outclock (~ARG[5]),
-    .outclocken (1'b1),~FI
+    .outclocken (~IF ~ISENABLED[7] ~THEN ~ARG[7] ~ELSE 1'b1 ~FI),
     .dataout (~RESULT),
     .aset (1'b0),
     .sset (1'b0),

clash-lib/prims/commonverilog/Clash_Signal_Internal.json

@@ -1,52 +1,42 @@
 [ { "BlackBox" :
-    { "name" : "Clash.Signal.Internal.clockGate"
+    { "name" : "Clash.Signal.Internal.toEnabledClock"
     , "kind" : "Declaration"
     , "type" :
-"clockGate
-  :: Clock domain gated -- ARG[0]
-  -> Signal domain Bool -- ARG[1]
-  -> Clock domain 'Gated"
+"toEnabledClock
+  :: Clock dom -- ARG[0]
+  -> Signal dom Bool -- ARG[1]
+  -> Clock dom"
     , "template" :
-"// clockGate begin~IF ~ISGATED[0] ~THEN
+"// toEnabledClock begin~IF ~ISENABLED[0] ~THEN
 assign ~RESULT = {~ARG[0][1],~ARG[0][0] & ~ARG[1]};~ELSE
 assign ~RESULT = {~ARG[0],~ARG[1]};~FI
-// clockGate end"
+// toEnabledClock end"
     }
   }
 , { "BlackBox" :
-    { "name"      : "Clash.Signal.Internal.unsafeFromAsyncReset"
+    { "name"      : "Clash.Signal.Internal.unsafeFromReset"
     , "workInfo"  : "Never"
     , "kind" : "Expression"
     , "type" :
-"unsafeFromAsyncReset :: Reset domain Asynchronous -> Signal domain Bool"
+"unsafeFromReset :: Reset dom -> Signal dom Bool"
     , "template" : "~ARG[0]"
     }
   }
 , { "BlackBox" :
-    { "name"      : "Clash.Signal.Internal.unsafeToAsyncReset"
-    , "workInfo"  : "Never"
+    { "name"      : "Clash.Signal.Internal.unsafeToReset"
     , "kind" : "Expression"
-    , "type" :
-"unsafeToAsyncReset :: Signal domain Bool -> Reset domain Asynchronous"
-    , "template" : "~ARG[0]"
-    }
-  }
-, { "BlackBox" :
-    { "name"      : "Clash.Signal.Internal.fromSyncReset"
     , "workInfo"  : "Never"
-    , "kind" : "Expression"
     , "type" :
-"fromSyncReset :: Reset domain Synchronous -> Signal domain Bool"
-    , "template" : "~ARG[0]"
+"unsafeToReset :: KnownDomain dom conf => Signal dom Bool -> Reset dom"
+    , "template" : "~ARG[1]"
     }
   }
 , { "BlackBox" :
-    { "name"      : "Clash.Signal.Internal.unsafeToSyncReset"
-    , "workInfo"  : "Never"
-    , "kind" : "Expression"
-    , "type" :
-"unsafeToSyncReset :: Signal domain Bool -> Reset domain Synchronous"
-    , "template" : "~ARG[0]"
+    { "name" : "Clash.Signal.Internal.tbEnableGen"
+    , "workInfo" : "Always"
+    , "kind" : "Declaration"
+    , "type" : "tbEnableGen :: Enable dom"
+    , "template" : "assign ~RESULT = 1'b1;"
     }
   }
 ]

clash-lib/prims/commonverilog/Clash_Xilinx_ClockGen.json

@@ -4,15 +4,17 @@
     , "kind"      : "Declaration"
     , "type"      :
 "clockWizard
-  :: SSymbol name               -- ARG[0]
-  -> Clock  pllIn 'Source       -- ARG[1]
-  -> Reset  pllIn 'Asynchronous -- ARG[2]
-  -> (Clock pllOut 'Source, Signal pllOut Bool)"
+  :: ( KnownDomain domIn confIn       -- ARG[0]
+     , KnownDomain domOut confOut )   -- ARG[1]
+  => SSymbol name                    -- ARG[2]
+  -> Clock  pllIn                    -- ARG[3]
+  -> Reset pllIn                     -- ARG[4]
+  -> (Clock pllOut, Enable pllOut)"
     , "template" :
 "// clockWizard begin
-~NAME[0] ~GENSYM[clockWizard_inst][2]
-(.CLK_IN1  (~ARG[1])
-,.RESET    (~ARG[2])
+~NAME[2] ~GENSYM[clockWizard_inst][2]
+(.CLK_IN1  (~ARG[3])
+,.RESET    (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[4])
 ,.CLK_OUT1 (~RESULT[1])
 ,.LOCKED   (~RESULT[0]));
 // clockWizard end"
@@ -24,17 +26,19 @@
     , "kind"      : "Declaration"
     , "type"      :
 "clockWizardDifferential
-  :: SSymbol name               -- ARG[0]
-  -> Clock  pllIn 'Source       -- ARG[1]
-  -> Clock  pllIn 'Source       -- ARG[2]
-  -> Reset  pllIn 'Asynchronous -- ARG[3]
-  -> (Clock pllOut 'Source, Signal pllOut Bool)"
+  :: ( KnownDomain domIn confIn       -- ARG[0]
+     , KnownDomain domOut confOut )   -- ARG[1]
+  :: SSymbol name                    -- ARG[2]
+  -> Clock  pllIn                    -- ARG[3]
+  -> Clock  pllIn                    -- ARG[4]
+  -> Reset pllIn                     -- ARG[5]
+  -> (Clock pllOut, Enable pllOut)"
     , "template" :
 "// clockWizardDifferential begin
-~NAME[0] ~GENSYM[clockWizardDifferential_inst][2]
-(.CLK_IN1_D_clk_n (~ARG[1])
-,.CLK_IN1_D_clk_n (~ARG[2])
-,.RESET           (~ARG[3])
+~NAME[2] ~GENSYM[clockWizardDifferential_inst][2]
+(.CLK_IN1_D_clk_n (~ARG[3])
+,.CLK_IN1_D_clk_n (~ARG[4])
+,.RESET           (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[5])
 ,.CLK_OUT1        (~RESULT[1])
 ,.LOCKED          (~RESULT[0]));
 // clockWizardDifferential end"

clash-lib/prims/systemverilog/Clash_Explicit_BlockRam.json

@@ -3,43 +3,44 @@
     , "kind" : "Declaration"
     , "type" :
 "blockRam#
-  :: HasCallStack    --       ARG[0]
-  => Undefined a     --       ARG[1]
-  => Clock dom gated -- clk,  ARG[2]
-  -> Vec n a         -- init, ARG[3]
-  -> Signal dom Int  -- rd,   ARG[4]
-  -> Signal dom Bool -- wren, ARG[5]
-  -> Signal dom Int  -- wr,   ARG[6]
-  -> Signal dom a    -- din,  ARG[7]
+  :: ( HasCallStack  --       ARG[0]
+     , Undefined a ) --       ARG[1]
+  => Clock dom       -- clk,  ARG[2]
+  -> Enable dom      -- en,   ARG[3]
+  -> Vec n a         -- init, ARG[4]
+  -> Signal dom Int  -- rd,   ARG[5]
+  -> Signal dom Bool -- wren, ARG[6]
+  -> Signal dom Int  -- wr,   ARG[7]
+  -> Signal dom a    -- din,  ARG[8]
   -> Signal dom a"
     , "template" :
 "// blockRam begin
-~SIGD[~GENSYM[RAM][0]][3];
-logic [~SIZE[~TYP[7]]-1:0] ~GENSYM[~RESULT_q][1];
+~SIGD[~GENSYM[RAM][0]][4];
+logic [~SIZE[~TYP[8]]-1:0] ~GENSYM[~RESULT_q][1];
 initial begin
-  ~SYM[0] = ~CONST[3];
-end~IF ~ISGATED[2] ~THEN
-always @(posedge ~ARG[2][1]) begin : ~GENSYM[~COMPNAME_blockRam][2]~IF ~VIVADO ~THEN
-  if (~ARG[2][0]) begin
-    if (~ARG[5]) begin
-      ~SYM[0][~ARG[6]] <= ~TOBV[~ARG[7]][~TYP[7]];
+  ~SYM[0] = ~CONST[4];
+end~IF ~ISENABLED[3] ~THEN
+always @(posedge ~ARG[2]) begin : ~GENSYM[~COMPNAME_blockRam][2]~IF ~VIVADO ~THEN
+  if (~ARG[3]) begin
+    if (~ARG[6]) begin
+      ~SYM[0][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
     end
-    ~SYM[1] <= ~SYM[0][~ARG[4]];
+    ~SYM[1] <= ~SYM[0][~ARG[5]];
   end~ELSE
-  if (~ARG[5] & ~ARG[2][0]) begin
-    ~SYM[0][~ARG[6]] <= ~TOBV[~ARG[7]][~TYP[7]];
+  if (~ARG[6] & ~ARG[3]) begin
+    ~SYM[0][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
   end
-  if (~ARG[2][0]) begin
-    ~SYM[1] <= ~SYM[0][~ARG[4]];
+  if (~ARG[3]) begin
+    ~SYM[1] <= ~SYM[0][~ARG[5]];
   end~FI
 end~ELSE
 always @(posedge ~ARG[2]) begin : ~SYM[2]
-  if (~ARG[5]) begin
-    ~SYM[0][~ARG[6]] <= ~TOBV[~ARG[7]][~TYP[7]];
+  if (~ARG[6]) begin
+    ~SYM[0][~ARG[7]] <= ~TOBV[~ARG[8]][~TYP[8]];
   end
-  ~SYM[1] <= ~SYM[0][~ARG[4]];
+  ~SYM[1] <= ~SYM[0][~ARG[5]];
 end~FI
-assign ~RESULT = ~FROMBV[~SYM[1]][~TYP[7]];
+assign ~RESULT = ~FROMBV[~SYM[1]][~TYP[8]];
 // blockRam end"
     }
   }

clash-lib/prims/systemverilog/Clash_Explicit_BlockRam_File.json

@@ -3,43 +3,45 @@
     , "kind" : "Declaration"
     , "type" :
 "blockRamFile#
-  :: (KnownNat m, HasCallStack)-- (ARG[0],ARG[1])
-  => Clock dom gated           -- clk,  ARG[2]
-  -> SNat n                    -- sz,   ARG[3]
-  -> FilePath                  -- file, ARG[4]
-  -> Signal dom Int            -- rd,   ARG[5]
-  -> Signal dom Bool           -- wren, ARG[6]
-  -> Signal dom Int            -- wr,   ARG[7]
-  -> Signal dom (BitVector m)  -- din,  ARG[8]
+  :: ( KnownNat m              --       ARG[0]
+    , HasCallStack )           --       ARG[1]
+  => Clock dom                 -- clk,  ARG[2]
+  => Enable dom                -- en,   ARG[3]
+  -> SNat n                    -- sz,   ARG[4]
+  -> FilePath                  -- file, ARG[5]
+  -> Signal dom Int            -- rd,   ARG[6]
+  -> Signal dom Bool           -- wren, ARG[7]
+  -> Signal dom Int            -- wr,   ARG[8]
+  -> Signal dom (BitVector m)  -- din,  ARG[9]
   -> Signal dom (BitVector m)"
     , "template" :
 "// blockRamFile begin
-~SIGDO[~GENSYM[RAM][0]] [0:~LIT[3]-1];
-~SIGD[~GENSYM[~RESULT_q][1]][8];
+~SIGDO[~GENSYM[RAM][0]] [0:~LIT[4]-1];
+~SIGD[~GENSYM[~RESULT_q][1]][9];
 
 initial begin
-  $readmemb(~FILE[~LIT[4]],~SYM[0]);
+  $readmemb(~FILE[~LIT[5]],~SYM[0]);
 end
-~IF ~ISGATED[2] ~THEN
-always @(posedge ~ARG[2][1]) begin : ~GENSYM[~COMPNAME_blockRamFile][2]~IF ~VIVADO ~THEN
-  if (~ARG[2][0]) begin
-    if (~ARG[6]) begin
-      ~SYM[0][~ARG[7]] <= ~ARG[8];
+~IF ~ISENABLED[3] ~THEN
+always @(posedge ~ARG[2]) begin : ~GENSYM[~COMPNAME_blockRamFile][2]~IF ~VIVADO ~THEN
+  if (~ARG[3]) begin
+    if (~ARG[7]) begin
+      ~SYM[0][~ARG[8]] <= ~ARG[9];
     end
-    ~SYM[1] <= ~SYM[0][~ARG[5]];
+    ~SYM[1] <= ~SYM[0][~ARG[6]];
   end~ELSE
-  if (~ARG[6] & ~ARG[2][0]) begin
-    ~SYM[0][~ARG[7]] <= ~ARG[8];
+  if (~ARG[7] & ~ARG[3]) begin
+    ~SYM[0][~ARG[8]] <= ~ARG[9];
   end
-  if (~ARG[2][0] begin
-    ~SYM[1] <= ~SYM[0][~ARG[5]];
+  if (~ARG[3]) begin
+    ~SYM[1] <= ~SYM[0][~ARG[6]];
   end~FI
 end~ELSE
 always @(posedge ~ARG[2]) begin : ~SYM[2]
-  if (~ARG[6]) begin
-    ~SYM[0][~ARG[7]] <= ~ARG[8];
+  if (~ARG[7]) begin
+    ~SYM[0][~ARG[8]] <= ~ARG[9];
   end
-  ~SYM[1] <= ~SYM[0][~ARG[5]];
+  ~SYM[1] <= ~SYM[0][~ARG[6]];
 end~FI
 
 assign ~RESULT = ~SYM[1];