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Verilog and System Verilog code gen bug for map head
#2809
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Thanks for the report. It's caused by the somewhat weird way that the blackboxes of function arguments to higher order blackboxes are handled. |
The way that way that blackboxes of function arguments to higher order blackboxes are handled is somewhat weird. For some reason, I don't fully understand, they're parsed, then de-parsed back into text, and later re-parsed again. This de-parsing didn't correctly re-escape previously escaped square brackets, causing the problem seen in #2809. Fixes #2809
The way that blackboxes of function arguments to higher order blackboxes are handled is somewhat weird. For some reason, I don't fully understand, they're parsed, then de-parsed back into text, and later re-parsed again. This de-parsing didn't correctly re-escape previously escaped square brackets, causing the problem seen in #2809. Fixes #2809
I first discovered the issue with Clash version 1.4.7 but it seems to still be around with the version of clash documented on
https://clash-lang.org/install/linux/
(stackage lts-19)Small repro code:
verilog
:system-verilog
:vhdl
(works):I realise that maybe that version is also outdated, but I can still reproduce on
master
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