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Update litex submodules; imports changed, does not compile.
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 * flash_proxies changed from c506426 to a628956
    * a628956 - Merge pull request timvideos#4 from cr1901/more-series7 <Robert Jördens>
    * 8be7e2d - Add new bitstream proxies for devices available as of Vivado 2017.4.1. <William D. Jones>
    * 29d9124 - Add new packages for missing Series 7 family members. <William D. Jones>
    * c1d8007 - Add missing Series 7 family members. <William D. Jones>

 * litedram changed from 13d41f6 to 48bc3cb
    * 48bc3cb - README: add migen dependency <Florent Kermarrec>
    * 697f46a - replace litex.gen imports with migen imports <Florent Kermarrec>
    * bd43fd6 - bump to 0.2.dev <Florent Kermarrec>
    * 45a948d - uniformize litex cores <Florent Kermarrec>
    * 5838953 - modules: add MT47H64M16 <Florent Kermarrec>
    * 57c63c1 - phy/a7ddrphy: make reset_n optional <Florent Kermarrec>
    * ec9ad2f - frontend/dma: add description of fifo_buffered parameter <Florent Kermarrec>

 * liteeth changed from 8fc7161 to 33afda7
    * 33afda7 - README: add migen dependency <Florent Kermarrec>
    * 79a6ba7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c15f089 - bump to 0.2.dev <Florent Kermarrec>
    * c42aa09 - uniformize litex cores <Florent Kermarrec>
    * 4e08d6e - Merge pull request timvideos#13 from felixheld/crc_pythonize <enjoy-digital>
    * 9dcc7bc - mac/crc.py: make crc calculation more pythonic <Felix Held>
    * 2ceaa74 - clarify the comments in mac/crc.py code <Felix Held>

 * litepcie changed from 945963d to 6b147e1
    * 6b147e1 - frontend/dma: add 16 bits control field to descriptors <Florent Kermarrec>
    * 08a4501 - README: add migen dependency <Florent Kermarrec>
    * 6afbd1c - frontend/dma/LitePCIeDMAWriter: switch to next decriptor when sink.last is asserted <Florent Kermarrec>
    * ed0b8a4 - phy/xilinx/7-series: integrate v3.3 files (working for x2) <Florent Kermarrec>
    * d9b8b2a - core/tlp/packetizer: add 128 bits support <Florent Kermarrec>
    * 686da6b - core/tlp/depacketizer: add 128 bits support <Florent Kermarrec>
    * 0724533 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3e38b54 - bump to 0.2.dev <Florent Kermarrec>
    * 96cdfe6 - revert phy to 3.0 and tlp packetizer/depacketizer to fixed 64 bit version (until we investigate the regression) <Florent Kermarrec>
    * d7d9e5f - uniformize litex cores <Florent Kermarrec>
    * 058c493 - phy/xilinx/7-series: update to 3.3 <Florent Kermarrec>
    * 98a2c77 - core/tlp/packetizer: typo <Florent Kermarrec>
    * d8bc19c - phy/s7pciephy: add x4 support (untested) <Florent Kermarrec>
    * 4609a88 - test/model/phy: fix typo <Florent Kermarrec>
    * a058223 - test/test_dma: remove converter parameter <Florent Kermarrec>
    * 525b843 - core/tlp/depacketizer: add 128 bits support (untested) <Florent Kermarrec>
    * 6210998 - core/tlp/packetizer: add 128 bits support (untested) <Florent Kermarrec>
    * 45227fe - example_designs/targets: fix dma target <Florent Kermarrec>
    * 7b5b806 - core/tlp/depacketizer: simplify using NextValue <Florent Kermarrec>

 * litesata changed from af00fa6 to a559afb
    * a559afb - README: add migen dependency <Florent Kermarrec>
    * c1e1341 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * eafaf16 - bump to 0.2.dev <Florent Kermarrec>
    * a6c08ce - uniformize litex cores <Florent Kermarrec>

 * litescope changed from aa44da3 to 9d5e605
    * 9d5e605 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 302a484 - bump to 0.2.dev <Florent Kermarrec>
    * 62c4bdd - uniformize litex cores <Florent Kermarrec>
    * 985585f - __init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports <Florent Kermarrec>

 * liteusb changed from 0b05b6c to 23d6a68
    * 23d6a68 - README: add migen dependency <Florent Kermarrec>
    * 102a751 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 3faa9ae - bump to 0.2.dev <Florent Kermarrec>
    * d52cf32 - uniformize litex cores <Florent Kermarrec>

 * litevideo changed from 9907975 to 18b88df
    * 18b88df - input/edid: fix scl polarity <Florent Kermarrec>
    * a3c1984 - README: add migen dependency <Florent Kermarrec>
    * 152b6d7 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * c96ef9c - bump to 0.2.dev <Florent Kermarrec>
    * 2274b01 - uniformize litex cores <Florent Kermarrec>
    * 50e8ac9 - output/VGAPHY: add missing self.sink.ready.eq(1) <Florent Kermarrec>
    * a7e289a - make split-clocking optional, also make output stage PLLE2 + BUFG <bunnie>
    * 78274ed - input/clocking: fix pix_o issue with spartan6 (will need cleaner fix) <Florent Kermarrec>
    * 61fa158 - Merge pull request timvideos#16 from MaZderMind/fix_hdmi_phy_cls_variable_name <Tim Ansell>
    * 96fdbec - Merge pull request timvideos#15 from bunnie/try_florent_720p <enjoy-digital>
    * a44b5d7 - tweak clocking parameters -- maybe marginally better? <bunnie>
    * 2d81c5b - fix phase relationship between master/slave MMCM <bunnie>
    * 9d99716 - these mods add a second MMCM, to fix the BUFG/BUFIO issue <bunnie>

 * litex changed from 4f272580 to 3e7cc255
    *   3e7cc255 - Merge pull request timvideos#69 from mithro/conda-support <enjoy-digital>
    |\
    | * 3bf50479 - travis: Adding some color. <Tim 'mithro' Ansell>
    | * 083c2613 - travis: Move the conda install into script so it can be folded. <Tim 'mithro' Ansell>
    | * da3189c8 - travis: Making the output more readable. <Tim 'mithro' Ansell>
    | * 12bb3ebf - travis: Build all the SoCs (without gateware). <Tim 'mithro' Ansell>
    | * e65c121a - Adding a travis config which tests the conda environment still works. <Tim 'mithro' Ansell>
    | * 795e8285 - Adding conda environment example. <Tim 'mithro' Ansell>
    |/
    *   ab2a3277 - Merge pull request timvideos#67 from cr1901/vivado-paths <enjoy-digital>
    |\
    | * 2b00b7eb - xilinx/vivado: Provide a fallback mechanism for using the same root for Vivado and ISE toolchains. <William D. Jones>
    * |   db20df49 - Merge pull request timvideos#65 from cr1901/tinyfpga-serial <enjoy-digital>
    |\ \
    | * | e71593d6 - platforms/tinyfpga_b: Move serial peripheral out of default I/O, make it optional via `add_extension`. <William D. Jones>
    * | | fa6b2561 - build/xilinx/platform: fix merge <Florent Kermarrec>
    * | |   87d4af0b - Merge pull request timvideos#66 from cr1901/arty_s7 <Tim Ansell>
    |\ \ \
    | * | | d40c5773 - boards/arty_s7: Fix IOStandard on System Clock. <William D. Jones>
    |/ / /
    * | | 7bd718eb - README: add migen installation to quick start guide <Florent Kermarrec>
    | |/
    |/|
    * | 0332f73a - build/xilinx/vivado: revert toolchain_path <Florent Kermarrec>
    * | 2ff50a88 - build: fix merge <Florent Kermarrec>
    * | 64e4e1ce - build: merge with migen.build 27beffe7 <Florent Kermarrec>
    * | 0edfd9b9 - boards/kcu105: regroup sfp tx and rx <Florent Kermarrec>
    |/
    * c5be6e26 - README: add section for newcomers <Florent Kermarrec>
    * f372e8c8 - README: cleanup <Florent Kermarrec>
    * fb088b79 - README: update, migen is no longer forked <Florent Kermarrec>
    * 1925ba17 - replace litex.gen imports with migen imports <Florent Kermarrec>
    * 43164b9a - remove migen fork from litex <Florent Kermarrec>
    * 212e1a70 - bump to 0.2.dev <Florent Kermarrec>
    * 64aa4ae4 - uniformize with litex cores and make things more clear about what LiteX vs Migen/MiSoC <Florent Kermarrec>
    *   aaf09705 - Merge pull request timvideos#64 from q3k/q3k/axi4lite <enjoy-digital>
    |\
    | * 688f26cc - Change AXI interface and tidy code <Sergiusz Bazanski>
    | * 512ed2b3 - Preliminary AXI4Lite CSR bridge support <Sergiusz Bazanski>
    |/
    *   55fc9d2d - Merge pull request timvideos#60 from q3k/for-upstream/top-level-module-selection <enjoy-digital>
    |\
    | * ef511e7e - Specify top-level module in Lattice Diemond build script. <Sergiusz Bazanski>
    | * ef6c517d - Build top module as 'dut' in Verilator and set it as top-level. <Sergiusz Bazanski>
    *   7b5bd404 - Merge pull request timvideos#57 from rohitk-singh/master <enjoy-digital>
    |\
    | * 75e7f950 - BIOS: Flashboot without main ram <Ewen McNeill>
    * c1450280 - board/targets/nexys4ddr: use MT47H64M16 <Florent Kermarrec>
    * 95ebba42 - boards/platforms/nexys4ddr: add user_sw, user_btn, fix ddr3 <Florent Kermarrec>
    * ee4fa597 - boards: add nexys4ddr <Florent Kermarrec>
    *   2ecd1b06 - Merge pull request timvideos#61 from PaulSchulz/master <enjoy-digital>
    |\
    | * 0ac35300 - Merge branch 'master' of https://github.com/enjoy-digital/litex into upstream <Paul Schulz>
    | * 3ac28ed6 - platform/arty.py: Move Pmod definitions to 'connectors' section. <Paul Schulz>
    * c83ae98b - Merge pull request timvideos#63 from cr1901/arty_s7 <enjoy-digital>
    * 4607e532 - boards/platforms: Add Arty S7 Board. <William D. Jones>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 48bc3cb15d17202a19e621acd83d2733190285b2 litedram (remotes/origin/HEAD)
 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD)
 6b147e1d120a3a062cf2c85e950d358b39edb8eb litepcie (remotes/origin/HEAD)
 a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD)
 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD)
 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD)
 18b88dfee6bf6f4ab55d196747ca00c6c84c2ef2 litevideo (remotes/origin/HEAD)
 3e7cc2554b7dcc578ca86fd881d3523625b888f8 litex (remotes/origin/HEAD)
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@cr1901 @mithro
cr1901 authored and mithro committed Mar 18, 2018
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Showing 9 changed files with 9 additions and 9 deletions.
2 changes: 1 addition & 1 deletion third_party/flash_proxies
Submodule flash_proxies updated from c50642 to a62895
2 changes: 1 addition & 1 deletion third_party/litedram
Submodule litedram updated 29 files
+89 −5 .gitignore
+3 −3 LICENSE
+29 −19 README
+6 −6 litedram/common.py
+2 −2 litedram/core/bankmachine.py
+1 −1 litedram/core/controller.py
+2 −2 litedram/core/multiplexer.py
+1 −1 litedram/core/perf.py
+2 −2 litedram/core/refresher.py
+1 −1 litedram/dfii.py
+1 −1 litedram/frontend/adaptation.py
+2 −2 litedram/frontend/bist.py
+1 −1 litedram/frontend/bridge.py
+2 −2 litedram/frontend/crossbar.py
+3 −3 litedram/frontend/dma.py
+16 −1 litedram/modules.py
+4 −2 litedram/phy/a7ddrphy.py
+7 −7 litedram/phy/dfi.py
+3 −3 litedram/phy/gensdrphy.py
+1 −1 litedram/phy/k7ddrphy.py
+2 −2 litedram/phy/kusddrphy.py
+1 −1 litedram/phy/model.py
+3 −3 litedram/phy/s6ddrphy.py
+4 −4 setup.py
+1 −1 test/common.py
+1 −1 test/test_bist.py
+1 −1 test/test_bist_async.py
+1 −1 test/test_downconverter.py
+2 −2 test/test_upconverter.py
2 changes: 1 addition & 1 deletion third_party/liteeth
Submodule liteeth updated 27 files
+30 −0 .gitignore
+1 −1 LICENSE
+35 −50 README
+2 −2 example_designs/make.py
+1 −1 example_designs/targets/base.py
+1 −1 example_designs/targets/core.py
+1 −1 liteeth/common.py
+2 −1 liteeth/core/arp.py
+2 −1 liteeth/core/mac/core.py
+6 −5 liteeth/core/mac/crc.py
+1 −1 liteeth/core/mac/preamble.py
+2 −1 liteeth/core/mac/wishbone.py
+2 −2 liteeth/phy/common.py
+2 −2 liteeth/phy/gmii.py
+2 −2 liteeth/phy/gmii_mii.py
+1 −1 liteeth/phy/mii.py
+4 −4 liteeth/phy/rmii.py
+4 −4 liteeth/phy/s6rgmii.py
+4 −4 liteeth/phy/s7rgmii.py
+4 −4 setup.py
+2 −1 test/test_arp.py
+2 −1 test/test_etherbone.py
+2 −1 test/test_icmp.py
+2 −1 test/test_ip.py
+2 −1 test/test_mac_core.py
+2 −1 test/test_mac_wishbone.py
+2 −1 test/test_udp.py
2 changes: 1 addition & 1 deletion third_party/litepcie
Submodule litepcie updated 64 files
+89 −5 .gitignore
+1 −1 LICENSE
+27 −43 README
+2 −2 example_designs/make.py
+10 −13 example_designs/targets/dma.py
+1 −1 litepcie/common.py
+1 −1 litepcie/core/common.py
+1 −1 litepcie/core/crossbar.py
+1 −1 litepcie/core/endpoint.py
+1 −1 litepcie/core/msi.py
+1 −1 litepcie/core/tlp/common.py
+2 −3 litepcie/core/tlp/controller.py
+92 −52 litepcie/core/tlp/depacketizer.py
+119 −41 litepcie/core/tlp/packetizer.py
+1 −1 litepcie/core/tlp/reordering.py
+26 −22 litepcie/frontend/dma.py
+1 −1 litepcie/frontend/wishbone.py
+5 −3 litepcie/phy/s7pciephy.py
+118 −58 litepcie/phy/xilinx/7-series/artix7/pcie_core_top.v
+28 −10 litepcie/phy/xilinx/7-series/common/pcie.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx_null_gen.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_rx_pipeline.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_top.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx_pipeline.v
+2 −1 litepcie/phy/xilinx/7-series/common/pcie_axi_basic_tx_thrtl_ctl.v
+5 −3 litepcie/phy/xilinx/7-series/common/pcie_gt_common.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_gt_rx_valid_filter_7x.v
+151 −150 litepcie/phy/xilinx/7-series/common/pcie_gt_top.v
+7 −11 litepcie/phy/xilinx/7-series/common/pcie_gt_wrapper.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_gtp_cpllpd_ovrd.v
+4 −4 litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_drp.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_rate.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_gtp_pipe_reset.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_gtx_cpllpd_ovrd.v
+65 −60 litepcie/phy/xilinx/7-series/common/pcie_pcie2_top.v
+12 −2 litepcie/phy/xilinx/7-series/common/pcie_pcie_7x.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_bram_7x.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_bram_top_7x.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_brams_7x.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_lane.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_misc.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pcie_pipe_pipeline.v
+20 −3 litepcie/phy/xilinx/7-series/common/pcie_pcie_top.v
+15 −14 litepcie/phy/xilinx/7-series/common/pcie_phy.v
+42 −19 litepcie/phy/xilinx/7-series/common/pcie_pipe_clock.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_drp.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_eq.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_rate.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_reset.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_sync.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_pipe_user.v
+512 −501 litepcie/phy/xilinx/7-series/common/pcie_pipe_wrapper.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_qpll_drp.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_qpll_reset.v
+83 −86 litepcie/phy/xilinx/7-series/common/pcie_qpll_wrapper.v
+1 −1 litepcie/phy/xilinx/7-series/common/pcie_rxeq_scan.v
+11 −4 litepcie/phy/xilinx/7-series/common/pcie_support.v
+1,285 −0 litepcie/phy/xilinx/7-series/common/xpm_cdc.sv
+3 −3 setup.py
+1 −1 test/model/phy.py
+6 −17 test/test_dma.py
+2 −1 test/test_wishbone.py
2 changes: 1 addition & 1 deletion third_party/litesata
Submodule litesata updated 15 files
+89 −5 .gitignore
+2 −3 LICENSE
+16 −47 README
+2 −2 example_designs/make.py
+2 −2 example_designs/targets/bist.py
+1 −1 example_designs/targets/core.py
+2 −2 example_designs/targets/mirroring.py
+3 −3 example_designs/targets/striping.py
+1 −1 litesata/common.py
+1 −1 litesata/frontend/arbitration.py
+1 −1 litesata/phy/ctrl.py
+1 −1 litesata/phy/datapath.py
+5 −5 litesata/phy/k7/crg.py
+2 −2 litesata/phy/k7/trx.py
+5 −4 setup.py
2 changes: 1 addition & 1 deletion third_party/litescope
Submodule litescope updated 10 files
+1 −1 LICENSE
+21 −27 README
+2 −2 example_designs/make.py
+2 −2 example_designs/targets/core.py
+2 −2 example_designs/targets/simple.py
+3 −1 litescope/__init__.py
+2 −2 litescope/core.py
+2 −1 litescope/software/driver/analyzer.py
+1 −1 setup.py
+1 −1 test/test_analyzer.py
2 changes: 1 addition & 1 deletion third_party/liteusb
Submodule liteusb updated from 0b05b6 to 23d6a6
2 changes: 1 addition & 1 deletion third_party/litevideo
Submodule litevideo updated from 990797 to 18b88d
2 changes: 1 addition & 1 deletion third_party/litex
Submodule litex updated 101 files

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