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asynchronous_fifo.v.out
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asynchronous_fifo.v.out
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_00000173ecd2fb50 .scope module, "asynchronous_fifo" "asynchronous_fifo" 2 7;
.timescale 0 0;
.port_info 0 /OUTPUT 8 "data_out";
.port_info 1 /OUTPUT 1 "full";
.port_info 2 /OUTPUT 1 "empty";
.port_info 3 /INPUT 8 "data_in";
.port_info 4 /INPUT 1 "wclk";
.port_info 5 /INPUT 1 "wrst_n";
.port_info 6 /INPUT 1 "rclk";
.port_info 7 /INPUT 1 "rrst_n";
.port_info 8 /INPUT 1 "w_en";
.port_info 9 /INPUT 1 "r_en";
P_00000173ecd168a0 .param/l "DATA_WIDTH" 0 2 7, +C4<00000000000000000000000000001000>;
P_00000173ecd168d8 .param/l "DEPTH" 0 2 7, +C4<00000000000000000000000000001000>;
P_00000173ecd16910 .param/l "PTR_WIDTH" 0 2 19, +C4<00000000000000000000000000000011>;
v00000173ecda1fe0_0 .net "b_rptr", 3 0, v00000173ecd9cf70_0; 1 drivers
v00000173ecda1ae0_0 .net "b_wptr", 3 0, v00000173ecda2440_0; 1 drivers
o00000173ecd4a858 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
v00000173ecda12c0_0 .net "data_in", 7 0, o00000173ecd4a858; 0 drivers
v00000173ecda2620_0 .net "data_out", 7 0, v00000173ecd449e0_0; 1 drivers
v00000173ecda2300_0 .net "empty", 0 0, v00000173ecd9d290_0; 1 drivers
v00000173ecda2120_0 .net "full", 0 0, v00000173ecda1900_0; 1 drivers
v00000173ecda2580_0 .net "g_rptr", 3 0, v00000173ecd9ca70_0; 1 drivers
v00000173ecda2bc0_0 .net "g_rptr_sync", 3 0, v00000173ecd9e190_0; 1 drivers
v00000173ecda1c20_0 .net "g_wptr", 3 0, v00000173ecda1a40_0; 1 drivers
v00000173ecda1540_0 .net "g_wptr_sync", 3 0, v00000173ecd9dfb0_0; 1 drivers
o00000173ecd4a918 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda1b80_0 .net "r_en", 0 0, o00000173ecd4a918; 0 drivers
o00000173ecd4a948 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda21c0_0 .net "rclk", 0 0, o00000173ecd4a948; 0 drivers
o00000173ecd4afd8 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda2da0_0 .net "rrst_n", 0 0, o00000173ecd4afd8; 0 drivers
o00000173ecd4a978 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda15e0_0 .net "w_en", 0 0, o00000173ecd4a978; 0 drivers
o00000173ecd4a9a8 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda2e40_0 .net "wclk", 0 0, o00000173ecd4a9a8; 0 drivers
o00000173ecd4b188 .functor BUFZ 1, C4<z>; HiZ drive
v00000173ecda1cc0_0 .net "wrst_n", 0 0, o00000173ecd4b188; 0 drivers
S_00000173ecd2fce0 .scope module, "fifom" "fifomemory" 2 56, 3 1 0, S_00000173ecd2fb50;
.timescale 0 0;
.port_info 0 /OUTPUT 8 "data_out";
.port_info 1 /INPUT 1 "empty";
.port_info 2 /INPUT 1 "full";
.port_info 3 /INPUT 1 "w_en";
.port_info 4 /INPUT 1 "r_en";
.port_info 5 /INPUT 8 "data_in";
.port_info 6 /INPUT 1 "wclk";
.port_info 7 /INPUT 1 "rclk";
.port_info 8 /INPUT 4 "b_wptr";
.port_info 9 /INPUT 4 "b_rptr";
P_00000173ecd2fe70 .param/l "DEPTH" 0 3 1, +C4<00000000000000000000000000001000>;
P_00000173ecd2fea8 .param/l "PTRWIDTH" 0 3 1, +C4<00000000000000000000000000000011>;
P_00000173ecd2fee0 .param/l "WIDTH" 0 3 1, +C4<00000000000000000000000000001000>;
v00000173ecd44760_0 .net "b_rptr", 3 0, v00000173ecd9cf70_0; alias, 1 drivers
v00000173ecd44e40_0 .net "b_wptr", 3 0, v00000173ecda2440_0; alias, 1 drivers
v00000173ecd44940_0 .net "data_in", 7 0, o00000173ecd4a858; alias, 0 drivers
v00000173ecd449e0_0 .var "data_out", 7 0;
v00000173ecd44120_0 .net "empty", 0 0, v00000173ecd9d290_0; alias, 1 drivers
v00000173ecd9cc50 .array "fifo", 7 0, 7 0;
v00000173ecd9d0b0_0 .net "full", 0 0, v00000173ecda1900_0; alias, 1 drivers
v00000173ecd9c930_0 .net "r_en", 0 0, o00000173ecd4a918; alias, 0 drivers
v00000173ecd9e230_0 .net "rclk", 0 0, o00000173ecd4a948; alias, 0 drivers
v00000173ecd9d150_0 .net "w_en", 0 0, o00000173ecd4a978; alias, 0 drivers
v00000173ecd9cb10_0 .net "wclk", 0 0, o00000173ecd4a9a8; alias, 0 drivers
E_00000173ecd1c5a0 .event posedge, v00000173ecd9e230_0;
E_00000173ecd1bca0 .event posedge, v00000173ecd9cb10_0;
S_00000173ecd35450 .scope module, "rptr_h" "readpointerhandler" 2 45, 4 2 0, S_00000173ecd2fb50;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "b_rptr";
.port_info 1 /OUTPUT 4 "g_rptr";
.port_info 2 /OUTPUT 1 "empty";
.port_info 3 /INPUT 4 "g_wptr_sync";
.port_info 4 /INPUT 1 "rrst_n";
.port_info 5 /INPUT 1 "rclk";
.port_info 6 /INPUT 1 "r_en";
P_00000173ecd1d120 .param/l "PTRWIDTH" 0 4 2, +C4<00000000000000000000000000000011>;
L_00000173ecd3c140 .functor AND 4, L_00000173ecda2800, L_00000173ecda6040, C4<1111>, C4<1111>;
v00000173ecd9e730_0 .net *"_ivl_0", 3 0, L_00000173ecda2800; 1 drivers
v00000173ecd9dbf0_0 .net *"_ivl_10", 3 0, L_00000173ecd3c140; 1 drivers
L_00000173ece10118 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v00000173ecd9da10_0 .net *"_ivl_3", 2 0, L_00000173ece10118; 1 drivers
v00000173ecd9ced0_0 .net *"_ivl_5", 0 0, L_00000173ecda28a0; 1 drivers
v00000173ecd9d5b0_0 .net *"_ivl_6", 3 0, L_00000173ecda6040; 1 drivers
L_00000173ece10160 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v00000173ecd9cd90_0 .net *"_ivl_9", 2 0, L_00000173ece10160; 1 drivers
v00000173ecd9cf70_0 .var "b_rptr", 3 0;
v00000173ecd9d010_0 .net "b_rptr_next", 3 0, L_00000173ecda5be0; 1 drivers
v00000173ecd9e4b0_0 .net "binary", 3 0, L_00000173ecda4920; 1 drivers
v00000173ecd9d290_0 .var "empty", 0 0;
v00000173ecd9ca70_0 .var "g_rptr", 3 0;
v00000173ecd9d330_0 .net "g_wptr_sync", 3 0, v00000173ecd9dfb0_0; alias, 1 drivers
v00000173ecd9e550_0 .net "r_en", 0 0, o00000173ecd4a918; alias, 0 drivers
v00000173ecd9df10_0 .net "rclk", 0 0, o00000173ecd4a948; alias, 0 drivers
v00000173ecd9d3d0_0 .net "rrst_n", 0 0, o00000173ecd4afd8; alias, 0 drivers
E_00000173ecd1d260/0 .event negedge, v00000173ecd9d3d0_0;
E_00000173ecd1d260/1 .event posedge, v00000173ecd9e230_0;
E_00000173ecd1d260 .event/or E_00000173ecd1d260/0, E_00000173ecd1d260/1;
L_00000173ecda2800 .concat [ 1 3 0 0], o00000173ecd4a918, L_00000173ece10118;
L_00000173ecda28a0 .reduce/nor v00000173ecd9d290_0;
L_00000173ecda6040 .concat [ 1 3 0 0], L_00000173ecda28a0, L_00000173ece10160;
L_00000173ecda5be0 .arith/sum 4, v00000173ecd9cf70_0, L_00000173ecd3c140;
S_00000173ecd355e0 .scope module, "uut" "g2bconverter2" 4 30, 5 1 0, S_00000173ecd35450;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "data_out";
.port_info 1 /INPUT 4 "data_in";
P_00000173ecd1cca0 .param/l "width" 0 5 1, +C4<000000000000000000000000000000100>;
v00000173ecd9d6f0_0 .net *"_ivl_16", 0 0, L_00000173ecda5dc0; 1 drivers
v00000173ecd9d790_0 .net "data_in", 3 0, v00000173ecd9dfb0_0; alias, 1 drivers
v00000173ecd9d8d0_0 .net "data_out", 3 0, L_00000173ecda4920; alias, 1 drivers
L_00000173ecda4ec0 .part L_00000173ecda4920, 3, 1;
L_00000173ecda42e0 .part v00000173ecd9dfb0_0, 2, 1;
L_00000173ecda4880 .part L_00000173ecda4920, 2, 1;
L_00000173ecda4e20 .part v00000173ecd9dfb0_0, 1, 1;
L_00000173ecda4f60 .part L_00000173ecda4920, 1, 1;
L_00000173ecda5d20 .part v00000173ecd9dfb0_0, 0, 1;
L_00000173ecda4920 .concat8 [ 1 1 1 1], L_00000173ecd3c3e0, L_00000173ecd3bf80, L_00000173ecd3c6f0, L_00000173ecda5dc0;
L_00000173ecda5dc0 .part v00000173ecd9dfb0_0, 3, 1;
S_00000173ece0dba0 .scope generate, "genblk1[0]" "genblk1[0]" 5 5, 5 5 0, S_00000173ecd355e0;
.timescale 0 0;
P_00000173ecd1cda0 .param/l "i" 0 5 5, +C4<00>;
L_00000173ecd3c3e0 .functor XOR 1, L_00000173ecda4f60, L_00000173ecda5d20, C4<0>, C4<0>;
v00000173ecd9e410_0 .net *"_ivl_0", 0 0, L_00000173ecda4f60; 1 drivers
v00000173ecd9ddd0_0 .net *"_ivl_1", 0 0, L_00000173ecda5d20; 1 drivers
v00000173ecd9d830_0 .net *"_ivl_2", 0 0, L_00000173ecd3c3e0; 1 drivers
S_00000173ece0dd30 .scope generate, "genblk1[1]" "genblk1[1]" 5 5, 5 5 0, S_00000173ecd355e0;
.timescale 0 0;
P_00000173ecd1cde0 .param/l "i" 0 5 5, +C4<01>;
L_00000173ecd3bf80 .functor XOR 1, L_00000173ecda4880, L_00000173ecda4e20, C4<0>, C4<0>;
v00000173ecd9ccf0_0 .net *"_ivl_0", 0 0, L_00000173ecda4880; 1 drivers
v00000173ecd9d1f0_0 .net *"_ivl_1", 0 0, L_00000173ecda4e20; 1 drivers
v00000173ecd9e690_0 .net *"_ivl_2", 0 0, L_00000173ecd3bf80; 1 drivers
S_00000173ecd2cd60 .scope generate, "genblk1[2]" "genblk1[2]" 5 5, 5 5 0, S_00000173ecd355e0;
.timescale 0 0;
P_00000173ecd1d320 .param/l "i" 0 5 5, +C4<010>;
L_00000173ecd3c6f0 .functor XOR 1, L_00000173ecda4ec0, L_00000173ecda42e0, C4<0>, C4<0>;
v00000173ecd9cbb0_0 .net *"_ivl_0", 0 0, L_00000173ecda4ec0; 1 drivers
v00000173ecd9de70_0 .net *"_ivl_1", 0 0, L_00000173ecda42e0; 1 drivers
v00000173ecd9ce30_0 .net *"_ivl_2", 0 0, L_00000173ecd3c6f0; 1 drivers
S_00000173ecd2cef0 .scope module, "sync_rptr" "two_fsynchroniser" 2 31, 6 1 0, S_00000173ecd2fb50;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "sync_out";
.port_info 1 /INPUT 4 "data_in";
.port_info 2 /INPUT 1 "clk";
.port_info 3 /INPUT 1 "reset_n";
P_00000173ecd1ce60 .param/l "WIDTH" 0 6 1, +C4<00000000000000000000000000000011>;
v00000173ecd9d970_0 .net "clk", 0 0, o00000173ecd4a9a8; alias, 0 drivers
v00000173ecd9c9d0_0 .net "data_in", 3 0, v00000173ecd9ca70_0; alias, 1 drivers
v00000173ecd9d470_0 .var "q1", 3 0;
v00000173ecd9dab0_0 .net "reset_n", 0 0, o00000173ecd4b188; alias, 0 drivers
v00000173ecd9e190_0 .var "sync_out", 3 0;
S_00000173ecd9f900 .scope module, "sync_wptr" "two_fsynchroniser" 2 30, 6 1 0, S_00000173ecd2fb50;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "sync_out";
.port_info 1 /INPUT 4 "data_in";
.port_info 2 /INPUT 1 "clk";
.port_info 3 /INPUT 1 "reset_n";
P_00000173ecd1cea0 .param/l "WIDTH" 0 6 1, +C4<00000000000000000000000000000011>;
v00000173ecd9e7d0_0 .net "clk", 0 0, o00000173ecd4a948; alias, 0 drivers
v00000173ecd9dc90_0 .net "data_in", 3 0, v00000173ecda1a40_0; alias, 1 drivers
v00000173ecd9db50_0 .var "q1", 3 0;
v00000173ecd9dd30_0 .net "reset_n", 0 0, o00000173ecd4afd8; alias, 0 drivers
v00000173ecd9dfb0_0 .var "sync_out", 3 0;
S_00000173ecda0aa0 .scope module, "wptr_h" "writepointerhandler" 2 34, 7 2 0, S_00000173ecd2fb50;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "b_wptr";
.port_info 1 /OUTPUT 4 "g_wptr";
.port_info 2 /OUTPUT 1 "full";
.port_info 3 /INPUT 4 "g_rptr_sync";
.port_info 4 /INPUT 1 "wrst_n";
.port_info 5 /INPUT 1 "wclk";
.port_info 6 /INPUT 1 "w_en";
P_00000173ecd1d3a0 .param/l "PTRWIDTH" 0 7 2, +C4<00000000000000000000000000000011>;
L_00000173ecd3cae0 .functor AND 4, L_00000173ecda26c0, L_00000173ecda1ea0, C4<1111>, C4<1111>;
v00000173ecda14a0_0 .net *"_ivl_0", 3 0, L_00000173ecda26c0; 1 drivers
v00000173ecda30c0_0 .net *"_ivl_10", 3 0, L_00000173ecd3cae0; 1 drivers
L_00000173ece10088 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v00000173ecda1e00_0 .net *"_ivl_3", 2 0, L_00000173ece10088; 1 drivers
v00000173ecda3160_0 .net *"_ivl_5", 0 0, L_00000173ecda2260; 1 drivers
v00000173ecda2b20_0 .net *"_ivl_6", 3 0, L_00000173ecda1ea0; 1 drivers
L_00000173ece100d0 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>;
v00000173ecda1400_0 .net *"_ivl_9", 2 0, L_00000173ece100d0; 1 drivers
v00000173ecda2440_0 .var "b_wptr", 3 0;
v00000173ecda2c60_0 .net "b_wptr_next", 3 0, L_00000173ecda2940; 1 drivers
v00000173ecda1720_0 .net "binary", 3 0, L_00000173ecda2760; 1 drivers
v00000173ecda1900_0 .var "full", 0 0;
v00000173ecda19a0_0 .net "g_rptr_sync", 3 0, v00000173ecd9e190_0; alias, 1 drivers
v00000173ecda1a40_0 .var "g_wptr", 3 0;
v00000173ecda3020_0 .net "w_en", 0 0, o00000173ecd4a978; alias, 0 drivers
v00000173ecda24e0_0 .net "wclk", 0 0, o00000173ecd4a9a8; alias, 0 drivers
v00000173ecda2d00_0 .net "wrst_n", 0 0, o00000173ecd4b188; alias, 0 drivers
E_00000173ecd1d3e0/0 .event negedge, v00000173ecd9dab0_0;
E_00000173ecd1d3e0/1 .event posedge, v00000173ecd9cb10_0;
E_00000173ecd1d3e0 .event/or E_00000173ecd1d3e0/0, E_00000173ecd1d3e0/1;
L_00000173ecda26c0 .concat [ 1 3 0 0], o00000173ecd4a978, L_00000173ece10088;
L_00000173ecda2260 .reduce/nor v00000173ecda1900_0;
L_00000173ecda1ea0 .concat [ 1 3 0 0], L_00000173ecda2260, L_00000173ece100d0;
L_00000173ecda2940 .arith/sum 4, v00000173ecda2440_0, L_00000173ecd3cae0;
S_00000173ecda0c30 .scope module, "uut2" "g2bconverter2" 7 34, 5 1 0, S_00000173ecda0aa0;
.timescale 0 0;
.port_info 0 /OUTPUT 4 "data_out";
.port_info 1 /INPUT 4 "data_in";
P_00000173ecd1d420 .param/l "width" 0 5 1, +C4<000000000000000000000000000000100>;
v00000173ecda17c0_0 .net *"_ivl_16", 0 0, L_00000173ecda1360; 1 drivers
v00000173ecda1860_0 .net "data_in", 3 0, v00000173ecd9e190_0; alias, 1 drivers
v00000173ecda2a80_0 .net "data_out", 3 0, L_00000173ecda2760; alias, 1 drivers
L_00000173ecda1f40 .part L_00000173ecda2760, 3, 1;
L_00000173ecda2ee0 .part v00000173ecd9e190_0, 2, 1;
L_00000173ecda1680 .part L_00000173ecda2760, 2, 1;
L_00000173ecda2f80 .part v00000173ecd9e190_0, 1, 1;
L_00000173ecda2080 .part L_00000173ecda2760, 1, 1;
L_00000173ecda23a0 .part v00000173ecd9e190_0, 0, 1;
L_00000173ecda2760 .concat8 [ 1 1 1 1], L_00000173ecd3be30, L_00000173ecd3bce0, L_00000173ecd3bc00, L_00000173ecda1360;
L_00000173ecda1360 .part v00000173ecd9e190_0, 3, 1;
S_00000173ecda0dc0 .scope generate, "genblk1[0]" "genblk1[0]" 5 5, 5 5 0, S_00000173ecda0c30;
.timescale 0 0;
P_00000173ecd1d460 .param/l "i" 0 5 5, +C4<00>;
L_00000173ecd3be30 .functor XOR 1, L_00000173ecda2080, L_00000173ecda23a0, C4<0>, C4<0>;
v00000173ecd9e050_0 .net *"_ivl_0", 0 0, L_00000173ecda2080; 1 drivers
v00000173ecd9d510_0 .net *"_ivl_1", 0 0, L_00000173ecda23a0; 1 drivers
v00000173ecd9d650_0 .net *"_ivl_2", 0 0, L_00000173ecd3be30; 1 drivers
S_00000173ecda0f50 .scope generate, "genblk1[1]" "genblk1[1]" 5 5, 5 5 0, S_00000173ecda0c30;
.timescale 0 0;
P_00000173ecd3a860 .param/l "i" 0 5 5, +C4<01>;
L_00000173ecd3bce0 .functor XOR 1, L_00000173ecda1680, L_00000173ecda2f80, C4<0>, C4<0>;
v00000173ecd9e5f0_0 .net *"_ivl_0", 0 0, L_00000173ecda1680; 1 drivers
v00000173ecd9e0f0_0 .net *"_ivl_1", 0 0, L_00000173ecda2f80; 1 drivers
v00000173ecd9e2d0_0 .net *"_ivl_2", 0 0, L_00000173ecd3bce0; 1 drivers
S_00000173ecda10e0 .scope generate, "genblk1[2]" "genblk1[2]" 5 5, 5 5 0, S_00000173ecda0c30;
.timescale 0 0;
P_00000173ecd3a520 .param/l "i" 0 5 5, +C4<010>;
L_00000173ecd3bc00 .functor XOR 1, L_00000173ecda1f40, L_00000173ecda2ee0, C4<0>, C4<0>;
v00000173ecd9e370_0 .net *"_ivl_0", 0 0, L_00000173ecda1f40; 1 drivers
v00000173ecda29e0_0 .net *"_ivl_1", 0 0, L_00000173ecda2ee0; 1 drivers
v00000173ecda1d60_0 .net *"_ivl_2", 0 0, L_00000173ecd3bc00; 1 drivers
.scope S_00000173ecd9f900;
T_0 ;
%wait E_00000173ecd1c5a0;
%load/vec4 v00000173ecd9dd30_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_0.0, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9db50_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9dfb0_0, 0;
%jmp T_0.1;
T_0.0 ;
%load/vec4 v00000173ecd9dc90_0;
%assign/vec4 v00000173ecd9db50_0, 0;
%load/vec4 v00000173ecd9db50_0;
%assign/vec4 v00000173ecd9dfb0_0, 0;
T_0.1 ;
%jmp T_0;
.thread T_0;
.scope S_00000173ecd2cef0;
T_1 ;
%wait E_00000173ecd1bca0;
%load/vec4 v00000173ecd9dab0_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_1.0, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9d470_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9e190_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v00000173ecd9c9d0_0;
%assign/vec4 v00000173ecd9d470_0, 0;
%load/vec4 v00000173ecd9d470_0;
%assign/vec4 v00000173ecd9e190_0, 0;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_00000173ecda0aa0;
T_2 ;
%wait E_00000173ecd1d3e0;
%load/vec4 v00000173ecda2d00_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_2.0, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecda2440_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecda1a40_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000173ecda1900_0, 0;
%jmp T_2.1;
T_2.0 ;
%load/vec4 v00000173ecda1900_0;
%nor/r;
%flag_set/vec4 9;
%flag_get/vec4 9;
%jmp/0 T_2.4, 9;
%load/vec4 v00000173ecda3020_0;
%and;
T_2.4;
%flag_set/vec4 8;
%jmp/0xz T_2.2, 8;
%load/vec4 v00000173ecda2c60_0;
%assign/vec4 v00000173ecda2440_0, 0;
%load/vec4 v00000173ecda2c60_0;
%load/vec4 v00000173ecda2c60_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%xor;
%assign/vec4 v00000173ecda1a40_0, 0;
T_2.2 ;
T_2.1 ;
%jmp T_2;
.thread T_2;
.scope S_00000173ecda0aa0;
T_3 ;
%wait E_00000173ecd1d3e0;
%load/vec4 v00000173ecda2440_0;
%parti/s 1, 3, 3;
%load/vec4 v00000173ecda1720_0;
%parti/s 1, 3, 3;
%cmp/ne;
%flag_get/vec4 4;
%load/vec4 v00000173ecda2440_0;
%parti/s 3, 0, 2;
%load/vec4 v00000173ecda1720_0;
%parti/s 3, 0, 2;
%cmp/e;
%flag_get/vec4 4;
%and;
%assign/vec4 v00000173ecda1900_0, 0;
%jmp T_3;
.thread T_3;
.scope S_00000173ecd35450;
T_4 ;
%wait E_00000173ecd1d260;
%load/vec4 v00000173ecd9d3d0_0;
%pad/u 32;
%cmpi/e 0, 0, 32;
%jmp/0xz T_4.0, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9cf70_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v00000173ecd9ca70_0, 0;
%jmp T_4.1;
T_4.0 ;
%load/vec4 v00000173ecd9d290_0;
%nor/r;
%load/vec4 v00000173ecd9e550_0;
%and;
%flag_set/vec4 8;
%jmp/0xz T_4.2, 8;
%load/vec4 v00000173ecd9d010_0;
%assign/vec4 v00000173ecd9cf70_0, 0;
%load/vec4 v00000173ecd9d010_0;
%load/vec4 v00000173ecd9d010_0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%xor;
%assign/vec4 v00000173ecd9ca70_0, 0;
T_4.2 ;
T_4.1 ;
%jmp T_4;
.thread T_4;
.scope S_00000173ecd35450;
T_5 ;
%wait E_00000173ecd1d260;
%load/vec4 v00000173ecd9cf70_0;
%load/vec4 v00000173ecd9e4b0_0;
%cmp/e;
%flag_get/vec4 4;
%assign/vec4 v00000173ecd9d290_0, 0;
%jmp T_5;
.thread T_5;
.scope S_00000173ecd2fce0;
T_6 ;
%wait E_00000173ecd1bca0;
%load/vec4 v00000173ecd9d150_0;
%load/vec4 v00000173ecd9d0b0_0;
%nor/r;
%and;
%flag_set/vec4 8;
%jmp/0xz T_6.0, 8;
%load/vec4 v00000173ecd44940_0;
%load/vec4 v00000173ecd44e40_0;
%pad/u 5;
%ix/vec4 3;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v00000173ecd9cc50, 0, 4;
T_6.0 ;
%jmp T_6;
.thread T_6;
.scope S_00000173ecd2fce0;
T_7 ;
%wait E_00000173ecd1c5a0;
%load/vec4 v00000173ecd9c930_0;
%load/vec4 v00000173ecd44120_0;
%nor/r;
%and;
%flag_set/vec4 8;
%jmp/0xz T_7.0, 8;
%load/vec4 v00000173ecd44760_0;
%pad/u 5;
%ix/vec4 4;
%load/vec4a v00000173ecd9cc50, 4;
%assign/vec4 v00000173ecd449e0_0, 0;
T_7.0 ;
%jmp T_7;
.thread T_7;
# The file index is used to find the file name in the following table.
:file_names 8;
"N/A";
"<interactive>";
"asynchronous_fifo.v";
"./fifomemory.v";
"./readpointerhandler.v";
"./g2bconverter2.v";
"./two_fsynchroniser.v";
"./writepointerhandler.v";