Introduction
An asynchronous FIFO (First-In-First-Out) is a type of data buffer that handles data transfers between two systems operating at different clock frequencies. This project implements an asynchronous FIFO using Verilog.

Features
Asynchronous read and write operations
Configurable FIFO depth and data width
Overflow and underflow protection
Full and empty status flags
Indivual testbenches for each Submodule

Implementation
Implementation of a circular Asynchronous FIFO Buffer has been made according to the block diagram given above
Wrap around condition is checked using an additional bit
Clock Domains have been synchronised using Two Flop Synchronisers
Conversions from Binary Code to Gray Code and vice versa have been implemented wherever necessary

Requirements:
Icarus Verilog
GTKWave

Contributing
Contributions are welcome! Please fork the repository and create a pull request with your changes. For major changes, please open an issue first to discuss what you would like to change.