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tb_readpointerhandler.vcd
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tb_readpointerhandler.vcd
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$date
Mon Jul 15 12:13:39 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb_readpointerhandler $end
$var wire 4 ! g_rd_ptr [3:0] $end
$var wire 1 " empty $end
$var wire 4 # b_rd_ptr [3:0] $end
$var parameter 32 $ PTRWIDTH $end
$var reg 4 % g_wptr_sync [3:0] $end
$var reg 1 & r_en $end
$var reg 1 ' rdclk $end
$var reg 1 ( read_reset_n $end
$scope module uut $end
$var wire 4 ) g_wptr_sync [3:0] $end
$var wire 1 & r_en $end
$var wire 1 ' rdclk $end
$var wire 1 ( read_reset_n $end
$var wire 4 * binary [3:0] $end
$var wire 4 + b_rd_ptr_next [3:0] $end
$var parameter 32 , PTRWIDTH $end
$var reg 4 - b_rd_ptr [3:0] $end
$var reg 1 " empty $end
$var reg 4 . g_rd_ptr [3:0] $end
$scope module uut $end
$var wire 4 / data_in [3:0] $end
$var wire 4 0 data_out [3:0] $end
$var parameter 33 1 width $end
$scope begin genblk1[0] $end
$var parameter 2 2 i $end
$upscope $end
$scope begin genblk1[1] $end
$var parameter 2 3 i $end
$upscope $end
$scope begin genblk1[2] $end
$var parameter 3 4 i $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10 4
b1 3
b0 2
b100 1
b11 ,
b11 $
$end
#0
$dumpvars
b0 0
b0 /
b0 .
b0 -
b0 +
b0 *
b0 )
0(
0'
0&
b0 %
b0 #
0"
b0 !
$end
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