Designed a SOC with the hardware capability of a Neural Network calculator which used to communicate with two different memories, one of which was for fetching weights and inputs to the calculator and other was to store the output result after the multiplication and summation.
- The design was divided into three pipelined modules to achieve high performance and reduce latency.
- The design was on implemented on 5 master/slave AHB bus model to control the flow of inputs,weights and outputs of neural network calculator.
- EDA Tool: Synopsys VCS, Language: SystemVerilog.