Skip to content
CI

Slang linter for Verilog. (#4713) #1910

Sign in to view logs

Slang linter for Verilog. (#4713)

Slang linter for Verilog. (#4713) #1910

Triggered via push February 22, 2024 02:18
@hsansonhsanson
pushed 52c6146
master
Status Success
Total duration 2m 39s
Artifacts –

main.yml

on: push
build_image
12s
build_image
Matrix: test_ale
Fit to window
Zoom out
Zoom in