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A simple design targeting iCE40 up5k with GHDL + Yosys.

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donnie-j/jcore-j1-ghdl

 
 

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A simple design targeting iCE40 up5k with GHDL + Yosys.

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  • VHDL 97.8%
  • Perl 1.8%
  • Makefile 0.4%