[RISC-V] Use common CodeGen::genHomeRegisterParams

src/coreclr/jit/abi.cpp

@@ -258,14 +258,16 @@ bool ABIPassingInformation::HasExactlyOneStackSegment() const
 //
 bool ABIPassingInformation::IsSplitAcrossRegistersAndStack() const
 {
-    bool anyReg   = false;
-    bool anyStack = false;
-    for (unsigned i = 0; i < NumSegments; i++)
+    if (NumSegments < 2)
+        return false;
+
+    bool isFirstInReg = Segments[0].IsPassedInRegister();
+    for (unsigned i = 1; i < NumSegments; i++)
     {
-        anyReg |= Segments[i].IsPassedInRegister();
-        anyStack |= Segments[i].IsPassedOnStack();
+        if (isFirstInReg != Segments[i].IsPassedInRegister())
+            return true;
     }
-    return anyReg && anyStack;
+    return false;
 }
 
 //-----------------------------------------------------------------------------

src/coreclr/jit/abi.h

@@ -51,8 +51,8 @@ struct ABIPassingInformation
     // - On loongarch64/riscv64, structs can be passed in two registers or
     // can be split out over register and stack, giving
     // multiple register segments and a struct segment.
-    unsigned           NumSegments = 0;
-    ABIPassingSegment* Segments    = nullptr;
+    unsigned           NumSegments;
+    ABIPassingSegment* Segments;
 
     ABIPassingInformation(unsigned numSegments = 0, ABIPassingSegment* segments = nullptr)
         : NumSegments(numSegments)

src/coreclr/jit/codegen.h

@@ -286,6 +286,8 @@ class CodeGen final : public CodeGenInterface
 
     void genHomeSwiftStructParameters(bool handleStack);
 
+    void genHomeStackPartOfSplitParameter(unsigned lclNum);
+
     void genCheckUseBlockInit();
 #if defined(UNIX_AMD64_ABI) && defined(FEATURE_SIMD)
     void genClearStackVec3ArgUpperBits();

src/coreclr/jit/codegencommon.cpp

@@ -2802,7 +2802,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 */
 
-#if !defined(TARGET_RISCV64)
 struct RegNode;
 
 struct RegNodeEdge
@@ -3069,6 +3068,7 @@ void CodeGen::genSpillOrAddRegisterParam(unsigned lclNum, RegGraph* graph)
 
     unsigned baseOffset = varDsc->lvIsStructField ? varDsc->lvFldOffset : 0;
     unsigned size       = varDsc->lvExactSize();
+    bool     isSpilled  = false;
 
     unsigned                     paramLclNum = varDsc->lvIsStructField ? varDsc->lvParentLcl : lclNum;
     LclVarDsc*                   paramVarDsc = compiler->lvaGetDesc(paramLclNum);
@@ -3102,6 +3102,7 @@ void CodeGen::genSpillOrAddRegisterParam(unsigned lclNum, RegGraph* graph)
 
             GetEmitter()->emitIns_S_R(ins_Store(storeType), emitActualTypeSize(storeType), seg.GetRegister(), lclNum,
                                       seg.Offset - baseOffset);
+            isSpilled = true;
         }
 
         if (!varDsc->lvIsInReg())
@@ -3138,6 +3139,11 @@ void CodeGen::genSpillOrAddRegisterParam(unsigned lclNum, RegGraph* graph)
             graph->AddEdge(sourceReg, destReg, edgeType, seg.Offset - baseOffset);
         }
     }
+
+    if (isSpilled)
+    {
+        genHomeStackPartOfSplitParameter(lclNum);
+    }
 }
 
 // -----------------------------------------------------------------------------
@@ -3157,6 +3163,8 @@ void CodeGen::genHomeRegisterParams(regNumber initReg, bool* initRegStillZeroed)
     }
 #endif
 
+    // RISC-V specific logic for homing the stack part of a split struct
+
     regMaskTP paramRegs = intRegState.rsCalleeRegArgMaskLiveIn | floatRegState.rsCalleeRegArgMaskLiveIn;
     if (compiler->opts.OptimizationDisabled())
     {
@@ -3181,6 +3189,8 @@ void CodeGen::genHomeRegisterParams(regNumber initReg, bool* initRegStillZeroed)
                                               lclNum, seg.Offset);
                 }
             }
+
+            genHomeStackPartOfSplitParameter(lclNum);
         }
 
         return;
@@ -3346,8 +3356,6 @@ void CodeGen::genHomeRegisterParams(regNumber initReg, bool* initRegStillZeroed)
     }
 }
 
-#endif
-
 // -----------------------------------------------------------------------------
 // genGetParameterHomingTempRegisterCandidates: Get the registers that are
 // usable during register homing.
@@ -4226,6 +4234,32 @@ void CodeGen::genHomeSwiftStructParameters(bool handleStack)
 }
 #endif
 
+/*-----------------------------------------------------------------------------
+ *
+ * Home the tail (stack) portion of a split parameter next to where the head (register) portion is homed.
+ *
+ * No-op on platforms where argument registers are already homed to form a contiguous space with incoming stack.
+ */
+void CodeGen::genHomeStackPartOfSplitParameter(unsigned lclNum)
+{
+#ifdef TARGET_RISCV64
+    const LclVarDsc* var = compiler->lvaGetDesc(lclNum);
+    if (!var->lvIsSplit)
+        return;
+
+    assert(varTypeIsStruct(var));
+    const ABIPassingInformation& abiInfo = compiler->lvaGetParameterABIInfo(lclNum);
+    assert(abiInfo.NumSegments == 2);
+    assert(abiInfo.Segments[0].GetRegister() == REG_ARG_LAST);
+    const ABIPassingSegment& seg = abiInfo.Segments[1];
+
+    int loadOffset =
+        -(isFramePointerUsed() ? genCallerSPtoFPdelta() : genCallerSPtoInitialSPdelta()) + (int)seg.GetStackOffset();
+    genInstrWithConstant(ins_Load(TYP_LONG), EA_8BYTE, REG_SCRATCH, genFramePointerReg(), loadOffset, REG_SCRATCH);
+    GetEmitter()->emitIns_S_R(ins_Store(TYP_LONG), EA_8BYTE, REG_SCRATCH, lclNum, seg.Offset);
+#endif
+}
+
 /*-----------------------------------------------------------------------------
  *
  *  Save the generic context argument.