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JIT ARM64-SVE: Add Compact API #102992

Merged
merged 2 commits into from
Jun 4, 2024
Merged

JIT ARM64-SVE: Add Compact API #102992

merged 2 commits into from
Jun 4, 2024

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mikabl-arm
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Tests results:

BEGIN EXECUTION
/home/mikabl01/dotnet/runtime/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false -p System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true HardwareIntrinsics_Arm_ro.dll 'Compact'
16:34:14.071 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_float()
Supported ISAs:
  AdvSimd:   True
  Aes:       True
  ArmBase:   True
  Crc32:     True
  Dp:        True
  Rdm:       True
  Sha1:      True
  Sha256:    True
  Sve:       True

Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.199 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_float()
16:34:14.220 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_double()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.249 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_double()
16:34:14.250 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_int()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.275 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_int()
16:34:14.276 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_long()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.303 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_long()
16:34:14.305 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_uint()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.330 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_uint()
16:34:14.332 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_ulong()
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask
Beginning scenario: ConditionalSelect_Op1_zero
Beginning scenario: ConditionalSelect_Op1_all
Beginning scenario: ConditionalSelect_Op2_mask
Beginning scenario: ConditionalSelect_Op2_zero
Beginning scenario: ConditionalSelect_Op2_all
Beginning scenario: ConditionalSelect_FalseOp_mask
Beginning scenario: ConditionalSelect_FalseOp_zero
Beginning scenario: ConditionalSelect_FalseOp_all
Beginning scenario: ConditionalSelect_ZeroOp_mask
Beginning scenario: ConditionalSelect_ZeroOp_zero
Beginning scenario: ConditionalSelect_ZeroOp_all
16:34:14.358 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_ulong()
Expected: 100
Actual: 100
END EXECUTION - PASSED

Stress tests results:

Starting test: /home/mikabl01/dotnet/runtime/artifacts/tests/coreclr/linux.arm64.Checked/Tests/Core_Root/corerun -p System.Reflection.Metadata.MetadataUpdater.IsSupported=false -p System.Runtime.Serialization.EnableUnsafeBinaryFormatterSerialization=true ./artifacts/tests/coreclr/linux.arm64.Checked/JIT/HardwareIntrinsics/HardwareIntrinsics_Arm_ro/HardwareIntrinsics_Arm_ro.dll Compact
===================Running default===================
------------------- {} -------------------
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_float() : 19
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_double() : 19
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_int() : 19
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_long() : 19
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_uint() : 19
Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_Compact_ulong() : 19
===================Running jitstress===================
------------------- {'JitMinOpts': '1'} -------------------
------------------- {'JitStress': '1'} -------------------
------------------- {'JitStress': '2'} -------------------
------------------- {'JitStress': '1', 'TieredCompilation': '1'} -------------------
------------------- {'JitStress': '2', 'TieredCompilation': '1'} -------------------
------------------- {'TailcallStress': '1'} -------------------
------------------- {'ReadyToRun': '0'} -------------------
===================Running jitstressregs===================
------------------- {'JitStressRegs': '1'} -------------------
------------------- {'JitStressRegs': '2'} -------------------
------------------- {'JitStressRegs': '3'} -------------------
------------------- {'JitStressRegs': '4'} -------------------
------------------- {'JitStressRegs': '8'} -------------------
------------------- {'JitStressRegs': '0x10'} -------------------
------------------- {'JitStressRegs': '0x80'} -------------------
------------------- {'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStressRegs': '0x2000'} -------------------
===================Running jitstress2-jitstressregs===================
------------------- {'JitStress': '2', 'JitStressRegs': '1'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '2'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '3'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '4'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '8'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x10'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x80'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x1000'} -------------------
------------------- {'JitStress': '2', 'JitStressRegs': '0x2000'} -------------------

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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Jun 3, 2024
@mikabl-arm
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@kunalspathak @dotnet/arm64-contrib @a74nh

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Tagging subscribers to this area: @dotnet/area-system-runtime-intrinsics
See info in area-owners.md if you want to be subscribed.

@kunalspathak kunalspathak mentioned this pull request Jun 3, 2024
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kunalspathak
kunalspathak requested changes Jun 3, 2024
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Overall looks good. Added some minor comments.

src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs
@@ -76,6 +78,22 @@
}
}";

const string SimpleVecOpTest_VectorValidationLogicForCndSel = @"
{
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do you mind sharing one of the generated test .cs file?

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Sure: Sve.Compact.float.cs.txt
(GitHub doesn't recognize .cs file format for some reason).

src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs Outdated Show resolved Hide resolved
src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs Show resolved Hide resolved
This was referenced Jun 3, 2024
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@kunalspathak kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Jun 4, 2024
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LGTM

@kunalspathak kunalspathak merged commit 909db28 into dotnet:main Jun 4, 2024
162 of 167 checks passed
@mikabl-arm mikabl-arm deleted the Compact-github branch June 4, 2024 14:32
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