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[Arm64] Use SIMD register to zero init frame #46609

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merged 14 commits into from
Jan 26, 2021
Merged

[Arm64] Use SIMD register to zero init frame #46609

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990e727
Refactor CodeGen::genZeroInitFrame in src/coreclr/jit/codegencommon.cpp
echesakov Jan 6, 2021
4450dfe
Use stp q9, q9, <addr-reg> for zeroing a frame in CodeGen::genZeroIni…
echesakov Jan 6, 2021
6c30e8c
Fix comment for CodeGen::genInstrWithConstant in src/coreclr/jit/code…
echesakov Jan 7, 2021
085a1c5
Leave the TARGET_ARM implementation of CodeGen::genZeroInitFrame asid…
echesakov Jan 7, 2021
4e6f31b
Format comment in CodeGen::genZeroInitFrame in src/coreclr/jit/codege…
echesakov Jan 7, 2021
c7e3936
Re-implement CodeGen::genZeroInitFrame() in src/coreclr/jit/codegenco…
echesakov Jan 8, 2021
a675e99
Implement GetDataCacheZeroIDReg() helper and use it to set Instructio…
echesakov Jan 20, 2021
062664e
Add InstructionSet_Dczva in src/coreclr/inc/corinfoinstructionset.h s…
echesakov Jan 20, 2021
5d10b15
Implement DC ZVA instruction in coreclr/jit/emitarm64.cpp src/coreclr…
echesakov Jan 20, 2021
527a5fc
Allow second operand of BFM instruction to be XZR or WZR in src/corec…
echesakov Jan 20, 2021
520e6db
Use DC ZVA for regions >= 320 bytes in src/coreclr/jit/codegencommon.…
echesakov Jan 20, 2021
7568476
Use DC ZVA for memory regions >= 256 bytes in src/coreclr/jit/codegen…
echesakov Jan 21, 2021
b472cc9
Update comment in CodeGen::genZeroInitFrame in src/coreclr/jit/codege…
echesakov Jan 26, 2021
2352f16
Update JIT/EE interface GUID in jiteeversionguid.h
echesakov Jan 26, 2021
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19 changes: 11 additions & 8 deletions src/coreclr/inc/corinfoinstructionset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -27,14 +27,15 @@ enum CORINFO_InstructionSet
InstructionSet_Atomics=9,
InstructionSet_Vector64=10,
InstructionSet_Vector128=11,
InstructionSet_ArmBase_Arm64=12,
InstructionSet_AdvSimd_Arm64=13,
InstructionSet_Aes_Arm64=14,
InstructionSet_Crc32_Arm64=15,
InstructionSet_Dp_Arm64=16,
InstructionSet_Rdm_Arm64=17,
InstructionSet_Sha1_Arm64=18,
InstructionSet_Sha256_Arm64=19,
InstructionSet_Dczva=12,
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You need to change the JIT/EE version GUID.

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Done

InstructionSet_ArmBase_Arm64=13,
InstructionSet_AdvSimd_Arm64=14,
InstructionSet_Aes_Arm64=15,
InstructionSet_Crc32_Arm64=16,
InstructionSet_Dp_Arm64=17,
InstructionSet_Rdm_Arm64=18,
InstructionSet_Sha1_Arm64=19,
InstructionSet_Sha256_Arm64=20,
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
InstructionSet_X86Base=1,
Expand Down Expand Up @@ -457,6 +458,8 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "Vector64";
case InstructionSet_Vector128 :
return "Vector128";
case InstructionSet_Dczva :
return "Dczva";
#endif // TARGET_ARM64
#ifdef TARGET_AMD64
case InstructionSet_X86Base :
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10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
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Expand Up @@ -32,11 +32,11 @@
//////////////////////////////////////////////////////////////////////////////////////////////////////////
//

constexpr GUID JITEEVersionIdentifier = { /* 000b3acb-92d2-4003-8760-e545241dd9a8 */
0x000b3acb,
0x92d2,
0x4003,
{0x87, 0x60, 0xe5, 0x45, 0x24, 0x1d, 0xd9, 0xa8}
constexpr GUID JITEEVersionIdentifier = { /* 960894e2-ec41-4088-82bb-bdcbac4ac2d3 */
0x960894e2,
0xec41,
0x4088,
{0x82, 0xbb, 0xbd, 0xcb, 0xac, 0x4a, 0xc2, 0xd3}
};

//////////////////////////////////////////////////////////////////////////////////////////////////////////
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3 changes: 2 additions & 1 deletion src/coreclr/jit/codegenarm64.cpp
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Expand Up @@ -54,7 +54,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Default: false.
//
// Return Value:
// returns true if the immediate was too large and tmpReg was used and modified.
// returns true if the immediate was small enough to be encoded inside instruction. If not,
// returns false meaning the immediate was too large and tmpReg was used and modified.
//
bool CodeGen::genInstrWithConstant(instruction ins,
emitAttr attr,
Expand Down
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