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ci test #60085

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ci test #60085

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eeac768
enable for arm64
EgorBo Oct 6, 2021
4264e34
fix small issue
EgorBo Oct 6, 2021
f144181
Update codegencommon.cpp
EgorBo Oct 6, 2021
b1ae6b0
Update codegencommon.cpp
EgorBo Oct 6, 2021
5e54adc
add ldr/str to r-r-r-i
EgorBo Oct 7, 2021
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15 changes: 6 additions & 9 deletions src/coreclr/jit/codegencommon.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1441,7 +1441,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,

cns += op2->AsIntConCommon()->IconValue();

#if defined(TARGET_ARMARCH)
#if defined(TARGET_ARM)
if (cns == 0)
#endif
{
Expand All @@ -1461,7 +1461,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,

goto AGAIN;

#if SCALED_ADDR_MODES && !defined(TARGET_ARMARCH)
#if SCALED_ADDR_MODES && !defined(TARGET_ARM)
// TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index.
case GT_MUL:
if (op1->gtOverflow())
Expand Down Expand Up @@ -1505,7 +1505,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,

switch (op1->gtOper)
{
#if !defined(TARGET_ARMARCH)
#if !defined(TARGET_ARM)
// TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index.
case GT_ADD:

Expand Down Expand Up @@ -1568,7 +1568,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
break;

#endif // SCALED_ADDR_MODES
#endif // !TARGET_ARMARCH
#endif // !TARGET_ARM

case GT_NOP:

Expand All @@ -1587,7 +1587,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
noway_assert(op2);
switch (op2->gtOper)
{
#if !defined(TARGET_ARMARCH)
#if !defined(TARGET_ARM)
// TODO-ARM64-CQ, TODO-ARM-CQ: For now we don't try to create a scaled index.
case GT_ADD:

Expand Down Expand Up @@ -1646,7 +1646,7 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,
break;

#endif // SCALED_ADDR_MODES
#endif // !TARGET_ARMARCH
#endif // !TARGET_ARM

case GT_NOP:

Expand All @@ -1666,9 +1666,6 @@ bool CodeGen::genCreateAddrMode(GenTree* addr,

rv1 = op1;
rv2 = op2;
#ifdef TARGET_ARM64
assert(cns == 0);
#endif

FOUND_AM:

Expand Down
5 changes: 5 additions & 0 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6459,6 +6459,11 @@ void emitter::emitIns_R_R_R_I(instruction ins,
/* Figure out the encoding format of the instruction */
switch (ins)
{
case INS_ldr:
case INS_str:
fmt = IF_LS_3A;
break;

case INS_extr:
assert(insOptsNone(opt));
assert(isValidGeneralDatasize(size));
Expand Down
25 changes: 2 additions & 23 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3030,7 +3030,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
// nodes with GTF_ADDRMODE_NO_CSE and calculate a more accurate cost.

addr->gtFlags |= GTF_ADDRMODE_NO_CSE;
#ifdef TARGET_XARCH
#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
// addrmodeCount is the count of items that we used to form
// an addressing mode. The maximum value is 4 when we have
// all of these: { base, idx, cns, mul }
Expand Down Expand Up @@ -3161,27 +3161,6 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
}
}
}
#elif defined TARGET_ARM64
if (base)
{
*pCostEx += base->GetCostEx();
*pCostSz += base->GetCostSz();
}

if (idx)
{
*pCostEx += idx->GetCostEx();
*pCostSz += idx->GetCostSz();
}

if (cns != 0)
{
if (cns >= (4096 * genTypeSize(type)))
{
*pCostEx += 1;
*pCostSz += 4;
}
}
#else
#error "Unknown TARGET"
#endif
Expand Down Expand Up @@ -3224,7 +3203,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
// we have already found either a non-ADD op1 or a non-constant op2.
gtWalkOp(&op1, &op2, nullptr, true);

#if defined(TARGET_XARCH)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
// For XARCH we will fold GT_ADDs in the op2 position into the addressing mode, so we call
// gtWalkOp on both operands of the original GT_ADD.
// This is not done for ARMARCH. Though the stated reason is that we don't try to create a
Expand Down