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[arm64] JIT: Make 0.0 containable for fcmp #61617

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Nov 16, 2021
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[arm64] JIT: Make 0.0 containable for fcmp #61617

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6a4db11
Make 0.0 containable for fcmp
EgorBo Nov 15, 2021
ba786f5
update comment
EgorBo Nov 15, 2021
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EgorBo Nov 15, 2021
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3 changes: 1 addition & 2 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3571,7 +3571,6 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
var_types op2Type = genActualType(op2->TypeGet());

assert(!op1->isUsedFromMemory());
assert(!op2->isUsedFromMemory());

genConsumeOperands(tree);

Expand All @@ -3585,7 +3584,7 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
assert(!op1->isContained());
assert(op1Type == op2Type);

if (op2->IsIntegralConst(0))
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@EgorBo So, effectively, this was always dead code, right?

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@echesakovMSFT yep

if (op2->IsFPZero())
{
assert(op2->isContained());
emit->emitIns_R_F(INS_fcmp, cmpSize, op1->GetRegNum(), 0.0);
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15 changes: 12 additions & 3 deletions src/coreclr/jit/lowerarmarch.cpp
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Expand Up @@ -48,13 +48,22 @@ bool Lowering::IsCallTargetInRange(void* addr)
// True if the immediate can be folded into an instruction,
// for example small enough and non-relocatable.
//
// TODO-CQ: we can contain a floating point 0.0 constant in a compare instruction
// (vcmp on arm, fcmp on arm64).
//
bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const
{
if (!varTypeIsFloating(parentNode->TypeGet()))
{
#ifdef TARGET_ARM64
if (parentNode->OperIsRelop() && childNode->IsFPZero())
{
// Contain 0.0 constant in fcmp on arm64
// TODO: Enable for arm too (vcmp)

// We currently don't emit these for floating points
assert(!parentNode->OperIs(GT_TEST_EQ, GT_TEST_NE));
return true;
}
#endif

// Make sure we have an actual immediate
if (!childNode->IsCnsIntOrI())
return false;
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