[LoongArch64] coreclr-jit directory

src/coreclr/gcinfo/CMakeLists.txt

@@ -75,6 +75,10 @@ if (CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_AMD64)
   create_gcinfo_lib(TARGET gcinfo_win_x64 OS win ARCH x64)
 endif (CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_AMD64)
 
+if (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+  create_gcinfo_lib(TARGET gcinfo_unix_loongarch64 OS unix ARCH loongarch64)
+endif (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+
 create_gcinfo_lib(TARGET gcinfo_universal_arm OS universal ARCH arm)
 create_gcinfo_lib(TARGET gcinfo_win_x86 OS win ARCH x86)
 

src/coreclr/inc/clrconfigvalues.h

@@ -745,7 +745,12 @@ RETAIL_CONFIG_DWORD_INFO(INTERNAL_GDBJitEmitDebugFrame, W("GDBJitEmitDebugFrame"
 //
 // Hardware Intrinsic ISAs
 //
+#if defined(TARGET_LOONGARCH64)
+//TODO: should implement LoongArch64's features.
+RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic,  W("EnableHWIntrinsic"),  0, "Allows Base+ hardware intrinsics to be disabled")
+#else
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic,  W("EnableHWIntrinsic"),  1, "Allows Base+ hardware intrinsics to be disabled")
+#endif // defined(TARGET_LOONGARCH64)
 
 #if defined(TARGET_AMD64) || defined(TARGET_X86)
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAES,          W("EnableAES"),          1, "Allows AES+ hardware intrinsics to be disabled")

src/coreclr/inc/crosscomp.h

@@ -399,7 +399,7 @@ enum
 
 #define CONTEXT_UNWOUND_TO_CALL 0x20000000
 
-typedef struct DECLSPEC_ALIGN(16) _T_CONTEXT {
+typedef struct DECLSPEC_ALIGN(8) _T_CONTEXT {
 
     //
     // Control flags.
@@ -414,8 +414,8 @@ typedef struct DECLSPEC_ALIGN(16) _T_CONTEXT {
     DWORD64 Ra;
     DWORD64 Tp;
     DWORD64 Sp;
-    DWORD64 A0;//DWORD64 V0;
-    DWORD64 A1;//DWORD64 V1;
+    DWORD64 A0;
+    DWORD64 A1;
     DWORD64 A2;
     DWORD64 A3;
     DWORD64 A4;
@@ -447,7 +447,7 @@ typedef struct DECLSPEC_ALIGN(16) _T_CONTEXT {
     //
     // Floating Point Registers
     //
-    //TODO: support the SIMD.
+    //TODO-LoongArch64: support the SIMD.
     DWORD64 F[32];
     DWORD   Fcsr;
 } T_CONTEXT, *PT_CONTEXT;
@@ -469,7 +469,6 @@ typedef struct _T_RUNTIME_FUNCTION {
     };
 } T_RUNTIME_FUNCTION, *PT_RUNTIME_FUNCTION;
 
-
 //
 // Define exception dispatch context structure.
 //
@@ -489,8 +488,6 @@ typedef struct _T_DISPATCHER_CONTEXT {
     PBYTE  NonVolatileRegisters;
 } T_DISPATCHER_CONTEXT, *PT_DISPATCHER_CONTEXT;
 
-
-
 //
 // Nonvolatile context pointer record.
 //

src/coreclr/inc/palclr.h

@@ -606,4 +606,8 @@
 
 #include "palclr_win.h"
 
+#ifndef IMAGE_FILE_MACHINE_LOONGARCH64
+#define IMAGE_FILE_MACHINE_LOONGARCH64       0x6264  // LOONGARCH64.
+#endif
+
 #endif // defined(HOST_WINDOWS)

src/coreclr/inc/targetosarch.h

@@ -41,27 +41,38 @@ class TargetArchitecture
     static const bool IsArm64 = false;
     static const bool IsArm32 = true;
     static const bool IsArmArch = true;
+    static const bool IsLoongArch64 = false;
 #elif defined(TARGET_ARM64)
     static const bool IsX86 = false;
     static const bool IsX64 = false;
     static const bool IsArm64 = true;
     static const bool IsArm32 = false;
     static const bool IsArmArch = true;
+    static const bool IsLoongArch64 = false;
 #elif defined(TARGET_AMD64)
     static const bool IsX86 = false;
     static const bool IsX64 = true;
     static const bool IsArm64 = false;
     static const bool IsArm32 = false;
     static const bool IsArmArch = false;
+    static const bool IsLoongArch64 = false;
 #elif defined(TARGET_X86)
     static const bool IsX86 = true;
     static const bool IsX64 = false;
     static const bool IsArm64 = false;
     static const bool IsArm32 = false;
     static const bool IsArmArch = false;
+    static const bool IsLoongArch64 = false;
+#elif defined(TARGET_LOONGARCH64)
+    static const bool IsX86 = false;
+    static const bool IsX64 = false;
+    static const bool IsArm64 = false;
+    static const bool IsArm32 = false;
+    static const bool IsArmArch = false;
+    static const bool IsLoongArch64 = true;
 #else
 #error Unknown architecture
 #endif
 };
 
-#endif // targetosarch_h
+#endif // targetosarch_h

src/coreclr/jit/CMakeLists.txt

@@ -44,6 +44,9 @@ function(create_standalone_jit)
   elseif(TARGETDETAILS_ARCH STREQUAL "s390x")
     set(JIT_ARCH_SOURCES ${JIT_S390X_SOURCES})
     set(JIT_ARCH_HEADERS ${JIT_S390X_HEADERS})
+  elseif(TARGETDETAILS_ARCH STREQUAL "loongarch64")
+    set(JIT_ARCH_SOURCES ${JIT_LOONGARCH64_SOURCES})
+    set(JIT_ARCH_HEADERS ${JIT_LOONGARCH64_HEADERS})
   else()
     clr_unknown_arch()
   endif()
@@ -233,6 +236,15 @@ set( JIT_S390X_SOURCES
   # Not supported as JIT target
 )
 
+set( JIT_LOONGARCH64_SOURCES
+  codegenloongarch64.cpp
+  emitloongarch64.cpp
+  lowerloongarch64.cpp
+  lsraloongarch64.cpp
+  targetloongarch64.cpp
+  unwindloongarch64.cpp
+)
+
 # We include the headers here for better experience in IDEs.
 set( JIT_HEADERS
   ../inc/corinfo.h
@@ -379,6 +391,13 @@ set ( JIT_S390X_HEADERS
   # Not supported as JIT target
 )
 
+set( JIT_LOONGARCH64_HEADERS
+    emitloongarch64.h
+    emitfmtsloongarch64.h
+    instrsloongarch64.h
+    registerloongarch64.h
+)
+
 convert_to_absolute_path(JIT_SOURCES ${JIT_SOURCES})
 convert_to_absolute_path(JIT_HEADERS ${JIT_HEADERS})
 convert_to_absolute_path(JIT_RESOURCES ${JIT_RESOURCES})
@@ -397,6 +416,8 @@ convert_to_absolute_path(JIT_ARMV6_SOURCES ${JIT_ARMV6_SOURCES})
 convert_to_absolute_path(JIT_ARMV6_HEADERS ${JIT_ARMV6_HEADERS})
 convert_to_absolute_path(JIT_S390X_SOURCES ${JIT_S390X_SOURCES})
 convert_to_absolute_path(JIT_S390X_HEADERS ${JIT_S390X_HEADERS})
+convert_to_absolute_path(JIT_LOONGARCH64_SOURCES ${JIT_LOONGARCH64_SOURCES})
+convert_to_absolute_path(JIT_LOONGARCH64_HEADERS ${JIT_LOONGARCH64_HEADERS})
 
 if(CLR_CMAKE_TARGET_ARCH_AMD64)
   set(JIT_ARCH_SOURCES ${JIT_AMD64_SOURCES})
@@ -416,6 +437,9 @@ elseif(CLR_CMAKE_TARGET_ARCH_ARM64)
 elseif(CLR_CMAKE_TARGET_ARCH_S390X)
   set(JIT_ARCH_SOURCES ${JIT_S390X_SOURCES})
   set(JIT_ARCH_HEADERS ${JIT_S390X_HEADERS})
+elseif(CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+  set(JIT_ARCH_SOURCES ${JIT_LOONGARCH64_SOURCES})
+  set(JIT_ARCH_HEADERS ${JIT_LOONGARCH64_HEADERS})
 else()
   clr_unknown_arch()
 endif()
@@ -558,6 +582,10 @@ if (CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_AMD64)
   create_standalone_jit(TARGET clrjit_win_x64_${ARCH_HOST_NAME} OS win ARCH x64 DESTINATIONS .)
 endif (CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_AMD64)
 
+if (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+  create_standalone_jit(TARGET clrjit_unix_loongarch64_${ARCH_HOST_NAME} OS unix ARCH loongarch64 DESTINATIONS .)
+endif (CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
+
 create_standalone_jit(TARGET clrjit_universal_arm_${ARCH_HOST_NAME} OS universal ARCH arm DESTINATIONS .)
 target_compile_definitions(clrjit_universal_arm_${ARCH_HOST_NAME} PRIVATE ARM_SOFTFP CONFIGURABLE_ARM_ABI)
 create_standalone_jit(TARGET clrjit_win_x86_${ARCH_HOST_NAME} OS win ARCH x86 DESTINATIONS .)

src/coreclr/jit/codegen.h

@@ -235,7 +235,16 @@ class CodeGen final : public CodeGenInterface
 
     void genJumpToThrowHlpBlk(emitJumpKind jumpKind, SpecialCodeKind codeKind, BasicBlock* failBlk = nullptr);
 
+#ifdef TARGET_LOONGARCH64
+    void genSetRegToIcon(regNumber reg, ssize_t val, var_types type);
+    void genJumpToThrowHlpBlk_la(SpecialCodeKind codeKind,
+                                 instruction     ins,
+                                 regNumber       reg1,
+                                 BasicBlock*     failBlk = nullptr,
+                                 regNumber       reg2    = REG_R0);
+#else
     void genCheckOverflow(GenTree* tree);
+#endif
 
     //-------------------------------------------------------------------------
     //
@@ -251,7 +260,11 @@ class CodeGen final : public CodeGenInterface
     //
 
     void genEstablishFramePointer(int delta, bool reportUnwindData);
+#if defined(TARGET_LOONGARCH64)
+    void genFnPrologCalleeRegArgs();
+#else
     void genFnPrologCalleeRegArgs(regNumber xtraReg, bool* pXtraRegClobbered, RegState* regState);
+#endif
     void genEnregisterIncomingStackArgs();
 #if defined(TARGET_ARM64)
     void genEnregisterOSRArgsAndLocals(regNumber initReg, bool* pInitRegZeroed);
@@ -263,7 +276,7 @@ class CodeGen final : public CodeGenInterface
     void genClearStackVec3ArgUpperBits();
 #endif // UNIX_AMD64_ABI && FEATURE_SIMD
 
-#if defined(TARGET_ARM64)
+#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
     bool genInstrWithConstant(instruction ins,
                               emitAttr    attr,
                               regNumber   reg1,
@@ -323,6 +336,7 @@ class CodeGen final : public CodeGenInterface
     void genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, int lowestCalleeSavedOffset, int spDelta);
 
     void genPushCalleeSavedRegisters(regNumber initReg, bool* pInitRegZeroed);
+
 #else
     void genPushCalleeSavedRegisters();
 #endif
@@ -408,7 +422,25 @@ class CodeGen final : public CodeGenInterface
 
     FuncletFrameInfoDsc genFuncletInfo;
 
-#endif // TARGET_AMD64
+#elif defined(TARGET_LOONGARCH64)
+
+    // A set of information that is used by funclet prolog and epilog generation.
+    // It is collected once, before funclet prologs and epilogs are generated,
+    // and used by all funclet prologs and epilogs, which must all be the same.
+    struct FuncletFrameInfoDsc
+    {
+        regMaskTP fiSaveRegs;                // Set of callee-saved registers saved in the funclet prolog (includes RA)
+        int fiFunction_CallerSP_to_FP_delta; // Delta between caller SP and the frame pointer in the parent function
+                                             // (negative)
+        int fiSP_to_FPRA_save_delta;         // FP/RA register save offset from SP (positive)
+        int fiSP_to_PSP_slot_delta;          // PSP slot offset from SP (positive)
+        int fiCallerSP_to_PSP_slot_delta;    // PSP slot offset from Caller SP (negative)
+        int fiFrameType;                     // Funclet frame types are numbered. See genFuncletProlog() for details.
+        int fiSpDelta1;                      // Stack pointer delta 1 (negative)
+    };
+
+    FuncletFrameInfoDsc genFuncletInfo;
+#endif // TARGET_LOONGARCH64
 
 #if defined(TARGET_XARCH)
 
@@ -598,6 +630,10 @@ class CodeGen final : public CodeGenInterface
     void genArm64EmitterUnitTests();
 #endif
 
+#if defined(DEBUG) && defined(TARGET_LOONGARCH64)
+    void genLoongArch64EmitterUnitTests();
+#endif
+
 #if defined(DEBUG) && defined(LATE_DISASM) && defined(TARGET_AMD64)
     void genAmd64EmitterUnitTests();
 #endif
@@ -1234,8 +1270,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genCodeForStoreLclFld(GenTreeLclFld* tree);
     void genCodeForStoreLclVar(GenTreeLclVar* tree);
     void genCodeForReturnTrap(GenTreeOp* tree);
-    void genCodeForJcc(GenTreeCC* tree);
-    void genCodeForSetcc(GenTreeCC* setcc);
     void genCodeForStoreInd(GenTreeStoreInd* tree);
     void genCodeForSwap(GenTreeOp* tree);
     void genCodeForCpObj(GenTreeObj* cpObjNode);
@@ -1324,7 +1358,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genTableBasedSwitch(GenTree* tree);
     void genCodeForArrIndex(GenTreeArrIndex* treeNode);
     void genCodeForArrOffset(GenTreeArrOffs* treeNode);
+#if defined(TARGET_LOONGARCH64)
+    instruction genGetInsForOper(GenTree* treeNode);
+#else
     instruction genGetInsForOper(genTreeOps oper, var_types type);
+#endif
     bool genEmitOptimizedGCWriteBarrier(GCInfo::WriteBarrierForm writeBarrierForm, GenTree* addr, GenTree* data);
     GenTree* getCallTarget(const GenTreeCall* call, CORINFO_METHOD_HANDLE* methHnd);
     regNumber getCallIndirectionCellReg(const GenTreeCall* call);
@@ -1333,7 +1371,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genJmpMethod(GenTree* jmp);
     BasicBlock* genCallFinally(BasicBlock* block);
     void genCodeForJumpTrue(GenTreeOp* jtrue);
-#ifdef TARGET_ARM64
+#if defined(TARGET_LOONGARCH64)
+    // TODO: refactor for LA.
+    void genCodeForJumpCompare(GenTreeOp* tree);
+#endif
+#if defined(TARGET_ARM64)
     void genCodeForJumpCompare(GenTreeOp* tree);
     void genCodeForMadd(GenTreeOp* tree);
     void genCodeForBfiz(GenTreeOp* tree);
@@ -1349,6 +1391,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genMultiRegStoreToSIMDLocal(GenTreeLclVar* lclNode);
     void genMultiRegStoreToLocal(GenTreeLclVar* lclNode);
 
+#if defined(TARGET_LOONGARCH64)
+    void genMultiRegCallStoreToLocal(GenTree* treeNode);
+#endif
+
     // Codegen for multi-register struct returns.
     bool isStructReturn(GenTree* treeNode);
 #ifdef FEATURE_SIMD
@@ -1364,9 +1410,9 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genFloatReturn(GenTree* treeNode);
 #endif // TARGET_X86
 
-#if defined(TARGET_ARM64)
+#if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64)
     void genSimpleReturn(GenTree* treeNode);
-#endif // TARGET_ARM64
+#endif // TARGET_ARM64 || TARGET_LOONGARCH64
 
     void genReturn(GenTree* treeNode);
 
@@ -1656,6 +1702,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     instruction genMapShiftInsToShiftByConstantIns(instruction ins, int shiftByValue);
 #endif // TARGET_XARCH
 
+#ifndef TARGET_LOONGARCH64
     // Maps a GenCondition code to a sequence of conditional jumps or other conditional instructions
     // such as X86's SETcc. A sequence of instructions rather than just a single one is required for
     // certain floating point conditions.
@@ -1699,6 +1746,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 
     void inst_JCC(GenCondition condition, BasicBlock* target);
     void inst_SETCC(GenCondition condition, var_types type, regNumber dstReg);
+
+    void genCodeForJcc(GenTreeCC* tree);
+    void genCodeForSetcc(GenTreeCC* setcc);
+#endif // !TARGET_LOONGARCH64
 };
 
 // A simple phase that just invokes a method on the codegen instance