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[JIT] X64 - Three instruction replacement sequence for multiply in certain cases #76981

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merged 25 commits into from
Oct 20, 2022
Merged

[JIT] X64 - Three instruction replacement sequence for multiply in certain cases #76981

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78c3247
Using 3 instruction sequence for x64 multiply
TIHan Oct 13, 2022
06a60e1
Do not do this in morph. Do it in codegen now.
TIHan Oct 13, 2022
7fb0095
Fixing codegen
TIHan Oct 13, 2022
86edb6c
Only allow values under 127 and do not skip mov - correctness testing
TIHan Oct 13, 2022
0955d11
Try to fix tests
TIHan Oct 13, 2022
865cf95
cleanup
TIHan Oct 13, 2022
999eac0
Moving to Lowering
TIHan Oct 14, 2022
6ebf58e
Quick fix
TIHan Oct 14, 2022
6e8f28c
Fully works in lowering now
TIHan Oct 14, 2022
94968a4
Account for all ints
TIHan Oct 14, 2022
64b523a
Take into account codegen opts
TIHan Oct 14, 2022
1cde9c0
Minor cleanup
TIHan Oct 14, 2022
c6fba6e
Minor cleanup
TIHan Oct 14, 2022
ff2b9a1
Fixed test
TIHan Oct 14, 2022
338dbe5
Added int multiply disasm checks. Fixed SuperFileCheck namespace bug.…
TIHan Oct 14, 2022
106c6b7
Update comments
TIHan Oct 14, 2022
8fc5b37
Update comments
TIHan Oct 14, 2022
e5835db
Update comments
TIHan Oct 14, 2022
3be48bf
Update comments
TIHan Oct 14, 2022
b3d4a5f
Formatting
TIHan Oct 15, 2022
843617a
Fixing build
TIHan Oct 16, 2022
74b1071
Fixing build again
TIHan Oct 17, 2022
90b7e7d
minor rename
TIHan Oct 17, 2022
214625f
Feedback. Removed use of FULL-LINE as it is more readable not strictl…
TIHan Oct 19, 2022
75313fb
Formatting
TIHan Oct 20, 2022
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13 changes: 13 additions & 0 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1106,6 +1106,19 @@ void CodeGen::genCodeForMul(GenTreeOp* treeNode)

inst_RV_SH(INS_shl, size, targetReg, shiftAmount);
}
#ifdef TARGET_AMD64
else if (!requiresOverflowCheck && rmOp->isUsedFromReg() && (imm <= 127) && isPow2(imm + 1))
{
uint64_t zextImm = static_cast<uint64_t>(static_cast<size_t>(imm + 1));
unsigned int shiftAmount = genLog2(zextImm );

inst_Mov(targetType, targetReg, rmOp->GetRegNum(), /* canSkip */ false);
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inst_RV_SH(INS_shl, size, targetReg, shiftAmount);

GetEmitter()->emitIns_R_R(INS_sub, emitTypeSize(treeNode->gtType), targetReg, rmOp->GetRegNum());
}
#endif
else
{
// use the 3-op form with immediate
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