[Mono][RISC-V] Lowering and output more OP for Regression test

src/mono/mono/arch/riscv/riscv-codegen.h

@@ -252,6 +252,21 @@ enum {
 	RISCV_ROUND_DY = 0b111, // Use current rounding mode in the FRM CSR.
 };
 
+enum {
+	RISCV_FCLASS_NINF = 0b1 << 0, // Negative infinity.
+	RISCV_FCLASS_NN = 0b1 << 1,   // Negative normal.
+	RISCV_FCLASS_ND = 0b1 << 2,   // Negative denormal.
+	RISCV_FCLASS_NZ = 0b1 << 3,   // Negative zero.
+	RISCV_FCLASS_PZ = 0b1 << 4,   // Positive zero.
+	RISCV_FCLASS_PD = 0b1 << 5,   // Positive denormal.
+	RISCV_FCLASS_PN = 0b1 << 6,   // Positive normal.
+	RISCV_FCLASS_PINF = 0b1 << 7, // Positive infinity.
+	RISCV_FCLASS_SNAN = 0b1 << 8, // Signalling NaN.
+	RISCV_FCLASS_QNAN = 0b1 << 9, // Quiet NaN.
+	RISCV_FCLASS_INF = RISCV_FCLASS_NINF | RISCV_FCLASS_PINF,
+	RISCV_FCLASS_NAN = RISCV_FCLASS_SNAN | RISCV_FCLASS_QNAN,
+};
+
 #define _riscv_emit(p, insn) \
 	do { \
 		*(guint32 *) (p) = (insn); \

src/mono/mono/mini/cpu-riscv64.mdesc

@@ -45,6 +45,7 @@ endfilter: src1:i len:32
 localloc: dest:i src1:i len:52
 localloc_imm: dest:i len:28
 generic_class_init: src1:a len:12 clob:c
+ckfinite: dest:f src1:f len:28
 break: len:4
 
 throw: src1:i len:4
@@ -63,23 +64,30 @@ vcall2: len:16 clob:c
 vcall2_reg: src1:i len:16 clob:c
 vcall2_membase: src1:b len:28 clob:c
 fcall: dest:f len:8 clob:c
-rcall: dest:f len:8 clob:c
-rcall_membase: dest:f src1:b len:12 clob:c
 fcall_reg: dest:f src1:i len:8 clob:c
 fcall_membase: dest:f src1:b len:12 clob:c
+rcall: dest:f len:8 clob:c
+rcall_reg: dest:f src1:i len:8 clob:c
+rcall_membase: dest:f src1:b len:12 clob:c
 
 # Note: in RV32, it shoule be 
 # lcall: dest:l ...
 lcall: dest:a len:16 clob:c
+lcall_reg: dest:a src1:i len:4 clob:c
 lcall_membase: dest:a src1:b len:8 clob:c
 
+tailcall_parameter: len:24
+tailcall: len:60 clob:c
+tailcall_membase: src1:b len:60 clob:c
+tailcall_reg: src1:b len:60 clob:c
+
 store_membase_reg: dest:b src1:i len:24
 storei1_membase_reg: dest:b src1:i len:24
 storei2_membase_reg: dest:b src1:i len:24
 storei4_membase_reg: dest:b src1:i len:24
 storei8_membase_reg: dest:b src1:i len:24
-storer4_membase_reg: dest:b src1:f len:4
-storer8_membase_reg: dest:b src1:f len:4
+storer4_membase_reg: dest:b src1:f len:24
+storer8_membase_reg: dest:b src1:f len:24
 
 load_membase: dest:i src1:b len:24
 loadu1_membase: dest:i src1:b len:24
@@ -89,18 +97,26 @@ loadi2_membase: dest:i src1:b len:24
 loadu4_membase: dest:i src1:b len:24
 loadi4_membase: dest:i src1:b len:24
 loadi8_membase: dest:i src1:b len:24
-loadr4_membase: dest:f src1:b len:16
-loadr8_membase: dest:f src1:b len:16
+loadr4_membase: dest:f src1:b len:24
+loadr8_membase: dest:f src1:b len:24
 
 memory_barrier: len:4
 atomic_add_i4: dest:i src1:i src2:i len:4
 atomic_add_i8: dest:i src1:i src2:i len:4
+atomic_store_i1: dest:b src1:i len:8
 atomic_store_u1: dest:b src1:i len:8
+atomic_store_i2: dest:b src1:i len:8
+atomic_store_u2: dest:b src1:i len:8
 atomic_store_i4: dest:b src1:i len:8
-atomic_store_u8: dest:b src1:i len:8
+atomic_store_u4: dest:b src1:i len:8
 atomic_store_i8: dest:b src1:i len:8
+atomic_store_u8: dest:b src1:i len:8
+atomic_load_i1: dest:b src1:i len:12
 atomic_load_u1: dest:b src1:i len:12
+atomic_load_i2: dest:b src1:i len:12
+atomic_load_u2: dest:b src1:i len:12
 atomic_load_i4: dest:b src1:i len:12
+atomic_load_u4: dest:b src1:i len:12
 atomic_load_i8: dest:b src1:i len:12
 atomic_load_u8: dest:b src1:i len:12
 atomic_cas_i4: dest:i src1:i src2:i src3:i len:24
@@ -112,48 +128,65 @@ move: dest:i src1:i len:4
 lmove: dest:i src1:i len:4
 fmove: dest:f src1:f len:4
 rmove: dest:f src1:f len:4
+move_f_to_i4: dest:i src1:f len:4
+move_i4_to_f: dest:f src1:i len:4
+move_f_to_i8: dest:i src1:f len:4
+move_i8_to_f: dest:f src1:i len:4
 
 iconst: dest:i len:16
-i8const: dest:i len:16
 int_add: dest:i src1:i src2:i len:4
-long_add: dest:i src1:i src2:i len:4
-float_add: dest:f src1:f src2:f len:4
 int_sub: dest:i src1:i src2:i len:4
-long_sub: dest:i src1:i src2:i len:4
-float_sub: dest:f src1:f src2:f len:4
-float_neg: dest:f src1:f len:4
 int_mul: dest:i src1:i src2:i len:4
-r4_mul: dest:f src1:f src2:f len:4
-long_mul: dest:i src1:i src2:i len:4
-float_mul: dest:f src1:f src2:f len:4
 int_div: dest:i src1:i src2:i len:32
-long_div: dest:i src1:i src2:i len:32
 int_div_un: dest:i src1:i src2:i len:32
-long_div_un: dest:i src1:i src2:i len:32
-r4_div: dest:f src1:f src2:f len:36
-float_div: dest:f src1:f src2:f len:36
 int_rem: dest:i src1:i src2:i len:32
-long_rem: dest:i src1:i src2:i len:32
 int_rem_un: dest:i src1:i src2:i len:32
+
+i8const: dest:i len:16
+long_add: dest:i src1:i src2:i len:4
+long_sub: dest:i src1:i src2:i len:4
+long_mul: dest:i src1:i src2:i len:4
+long_div: dest:i src1:i src2:i len:32
+long_div_un: dest:i src1:i src2:i len:32
+long_rem: dest:i src1:i src2:i len:32
 long_rem_un: dest:i src1:i src2:i len:32
 
-r4const: dest:f len:16
 r8const: dest:f len:16
+float_neg: dest:f src1:f len:4
+float_add: dest:f src1:f src2:f len:4
+float_sub: dest:f src1:f src2:f len:4
+float_mul: dest:f src1:f src2:f len:4
+float_div: dest:f src1:f src2:f len:36
+
+r4const: dest:f len:16
+r4_neg: dest:f src1:f len:4
+r4_add: dest:f src1:f src2:f len:4
+r4_sub: dest:f src1:f src2:f len:4
+r4_mul: dest:f src1:f src2:f len:4
+r4_div: dest:f src1:f src2:f len:36
+
+
 int_conv_to_r4: dest:f src1:i len:4
 int_conv_to_r8: dest:f src1:i len:4
 r4_conv_to_i8: dest:i src1:f len:4
 r4_conv_to_r8: dest:f src1:f len:4
 r4_conv_to_i4: dest:i src1:f len:4
+r4_conv_to_u4: dest:i src1:f len:4
+r4_conv_to_u8: dest:i src1:f len:4
 float_conv_to_i4: dest:i src1:f len:4
+float_conv_to_u4: dest:i src1:f len:4
 float_conv_to_r4: dest:f src1:f len:4
 float_conv_to_i8: dest:i src1:f len:4
+float_conv_to_u8: dest:i src1:f len:4
+
+r4_ceq: dest:i src1:f src2:f len:4
+r4_clt: dest:i src1:f src2:f len:4
+r4_clt_un: dest:i src1:f src2:f len:4
+r4_cle: dest:i src1:f src2:f len:4
 float_ceq: dest:i src1:f src2:f len:4
 float_cle: dest:i src1:f src2:f len:4
 float_clt: dest:i src1:f src2:f len:4
 float_clt_un: dest:i src1:f src2:f len:4
-r4_clt: dest:i src1:f src2:f len:4
-r4_clt_un: dest:i src1:f src2:f len:4
-r4_cle: dest:i src1:f src2:f len:4
 
 add_imm: dest:i src1:i len:4
 int_add_imm: dest:i src1:i len:4
@@ -182,27 +215,31 @@ long_and: dest:i src1:i src2:i len:4
 long_and_imm: dest:i src1:i len:4
 long_or: dest:i src1:i src2:i len:4
 long_xor: dest:i src1:i src2:i len:4
+long_xor_imm: dest:i src1:i len:4
 long_or_imm: dest:i src1:i len:4
 long_shl: dest:i src1:i src2:i len:4
 long_shl_imm: dest:i src1:i len:4
+long_shr: dest:i src1:i src2:i len:4
 long_shr_un: dest:i src1:i src2:i len:4
 long_shr_imm: dest:i src1:i len:4
 long_shr_un_imm: dest:i src1:i len:4
 
 
 riscv_setfreg_r4: dest:f src1:f len:4
+riscv_float_bnan: src1:f len:16
+riscv_r4_bnan: src1:f len:16
 
 riscv_beq: src1:i src2:i len:8
 riscv_bne: src1:i src2:i len:8
 riscv_bge: src1:i src2:i len:8
 riscv_bgeu: src1:i src2:i len:8
 riscv_blt: src1:i src2:i len:8
 riscv_bltu: src1:i src2:i len:8
-riscv_exc_beq: src1:i src2:i len:12
-riscv_exc_bne: src1:i src2:i len:12
-riscv_exc_bgeu: src1:i src2:i len:12
-riscv_exc_blt: src1:i src2:i len:12
-riscv_exc_bltu: src1:i src2:i len:12
+riscv_exc_beq: src1:i src2:i len:16
+riscv_exc_bne: src1:i src2:i len:16
+riscv_exc_bgeu: src1:i src2:i len:16
+riscv_exc_blt: src1:i src2:i len:16
+riscv_exc_bltu: src1:i src2:i len:16
 riscv_slt: dest:i src1:i src2:i len:4
 riscv_sltu: dest:i src1:i src2:i len:4
 riscv_slti: dest:i src1:i len:4

src/mono/mono/mini/exceptions-riscv.c

@@ -83,7 +83,7 @@ mono_riscv_throw_exception (gpointer arg, host_mgreg_t pc, host_mgreg_t *int_reg
 	}
 
 	/* Adjust pc so it points into the call instruction */
-	pc -= 4;
+	pc--;
 
 	/* Initialize a ctx based on the arguments */
 	memset (&ctx, 0, sizeof (MonoContext));
@@ -114,7 +114,7 @@ mono_arch_get_call_filter (MonoTrampInfo **info, gboolean aot)
 {
 	guint8 *code;
 	guint8 *start;
-	int i, size, offset, gregs_offset, fregs_offset, ctx_offset, num_fregs, frame_size;
+	int size, offset, gregs_offset, fregs_offset, ctx_offset, frame_size;
 	MonoJumpInfo *ji = NULL;
 	GSList *unwind_ops = NULL;
 

src/mono/mono/mini/mini-ops.h

@@ -1889,6 +1889,8 @@ MINI_OP(OP_RISCV_BGE, "riscv_bge", NONE, IREG, IREG)
 MINI_OP(OP_RISCV_BGEU, "riscv_bgeu", NONE, IREG, IREG)
 MINI_OP(OP_RISCV_BLT, "riscv_blt", NONE, IREG, IREG)
 MINI_OP(OP_RISCV_BLTU, "riscv_bltu", NONE, IREG, IREG)
+MINI_OP(OP_RISCV_RBNAN, "riscv_r4_bnan", NONE, FREG, NONE)
+MINI_OP(OP_RISCV_FBNAN, "riscv_float_bnan", NONE, FREG, NONE)
 
 MINI_OP(OP_RISCV_ADDIW, "riscv_addiw", IREG, IREG, NONE)