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Cortex-M7 : Is _tx_thread_context_save/_tx_thread_context_restore required in interrupts? #381
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Not manually, For Armv7-M ISA based CPU like Cortex-M7, caller save registers (r0-r3,r12,LR(r14),PC(r15), xPSR) would be saved into stack by hardware, and r4-r9, r10,r11,SP would be saved by callee functions, save and restore instructions would be generated by compilers, so for C programmers, no manual procedure is required to save/restore contexts. |
Hi @rayc345 |
@amgross Thank you for the reply. Honestly, I've been working with ThreadX for 3 years now without doing this, and I've yet to see anything that is obviously wrong. |
Hi @maxkunes , |
I do not call it at all.
…On Sat, May 18, 2024 at 10:21 PM amgross ***@***.***> wrote:
Hi @maxkunes <https://github.com/maxkunes> ,
By 'without doing it' you mean you call it from C code or not calling it
at all?
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Surprisingly (for me), it seems like I was mistaken and there is no need for cortex M to use save/restore threadx/ports/cortex_m7/ac5/readme_threadx.txt Lines 161 to 173 in 485a02f
So @rayc345 is correct |
But that seems to depend on the compiler used?
See:
https://github.com/eclipse-threadx/threadx/blob/485a02faec6edccef14812ddce6844af1d7d2eef/ports/cortex_m7/gnu/readme_threadx.txt
Which says on GNU you have to use assembly to save r0 and lr and then you
can bl to your C function.
Im using arm-none-eabi-gcc, which presumably is AC5 or 6? If so, that
explains why I don't have issues.
…On Sun, May 19, 2024 at 2:33 AM amgross ***@***.***> wrote:
Surprisingly (for me), it seems like I was mistaken and there is no need
for cortex M to use save/restore
https://github.com/eclipse-threadx/threadx/blob/485a02faec6edccef14812ddce6844af1d7d2eef/ports/cortex_m7/ac5/readme_threadx.txt#L161-L173
So @rayc345 <https://github.com/rayc345> is correct
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The ThreadX docs under Chapter 3 - Functional Components: ISR Template suggest that context saving and restoring must be done in assembly before executing any ThreadX code (i.e. notifying semaphores) or calling user code.
Is this required on Cortex-M7? Or is this only needed on specific architectures?
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