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AArch64: Add variants of vector shift instructions #6784

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Nov 16, 2022
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AArch64: Add variants of vector shift instructions #6784

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18 changes: 16 additions & 2 deletions compiler/aarch64/codegen/ARM64Debug.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -758,14 +758,28 @@ static const char *opCodeToNameMap[] =
"vushll2_8h",
"vushll2_4s",
"vushll2_2d",
"vsli16b",
"vsli8h",
"vsli4s",
"vsli2d",
"vsshr16b",
"vsshr8h",
"vsshr4s",
"vsshr2d",
"vshrn_8b",
"vshrn_4h",
"vshrn_2s",
"vshrn2_16b",
"vshrn2_8h",
"vshrn2_4s",
"vushr16b",
"vushr8h",
"vushr4s",
"vushr2d",
"vsri16b",
"vsri8h",
"vsri4s",
"vsri2d",
"vshll_8h",
"vshll_4s",
"vshll_2d",
Expand Down Expand Up @@ -1863,10 +1877,10 @@ TR_Debug::print(TR::FILE *pOutFile, TR::ARM64Trg1Src1ImmInstruction *instr)
}
}
}
else if ((op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vushr2d))
else if ((op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vsri2d))
{
done = true;
bool isShiftLeft = (op <= TR::InstOpCode::vushll2_2d);
bool isShiftLeft = (op <= TR::InstOpCode::vsli2d);
uint32_t immh = (TR::InstOpCode::getOpCodeBinaryEncoding(op) >> 19) & 0xf;
uint32_t elementSize = 8 << (31 - leadingZeroes(immh));
uint32_t imm = instr->getSourceImmediate();
Expand Down
2 changes: 1 addition & 1 deletion compiler/aarch64/codegen/ARM64Instruction.hpp
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Expand Up @@ -2326,7 +2326,7 @@ class ARM64Trg1Src1ImmInstruction : public ARM64Trg1Src1Instruction
{
TR::InstOpCode::Mnemonic op = getOpCodeValue();

if ((op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vushr2d))
if ((op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vsri2d))
{
*instruction |= ((_source1Immediate & 0x7f) << 16); /* immh:immb */
}
Expand Down
13 changes: 9 additions & 4 deletions compiler/aarch64/codegen/GenerateInstructions.cpp
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Expand Up @@ -637,13 +637,18 @@ TR::Instruction *generateUBFIZInstruction(TR::CodeGenerator *cg, TR::Node *node,
TR::Instruction *generateVectorShiftImmediateInstruction(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic op, TR::Node *node,
TR::Register *treg, TR::Register *sreg, uint32_t shiftAmount, TR::Instruction *preced)
{
TR_ASSERT_FATAL_WITH_NODE(node, (op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vushr2d), "Illegal opcode for generateVectorShiftImmediateInstruction: %d", op);
TR_ASSERT_FATAL_WITH_NODE(node, (op >= TR::InstOpCode::vshl16b) && (op <= TR::InstOpCode::vsri2d), "Illegal opcode for generateVectorShiftImmediateInstruction: %d", op);

bool isShiftLeft = (op <= TR::InstOpCode::vushll2_2d);
uint32_t immh = (TR::InstOpCode::getOpCodeBinaryEncoding(op) >> 19) & 0xf;
bool isShiftLeft = (op <= TR::InstOpCode::vsli2d);
const auto opcodeBinaryEncoding = TR::InstOpCode::getOpCodeBinaryEncoding(op);
/* If bit 11 - 15 is 0b100xx, then it is a variant of shift right narrow instructions. */
const bool isShiftRightNarrow = ((opcodeBinaryEncoding >> 11) & 0x1c) == 0x10;
uint32_t immh = (opcodeBinaryEncoding >> 19) & 0xf;
uint32_t elementSize = 8 << (31 - leadingZeroes(immh));
TR_ASSERT_FATAL_WITH_NODE(node, (elementSize == 8) || (elementSize == 16) || (elementSize == 32) || (elementSize == 64), "Illegal element size: %d", elementSize);
TR_ASSERT_FATAL_WITH_NODE(node, (shiftAmount >= 0) && (shiftAmount < elementSize), "Illegal shift amount: %d", shiftAmount);
const uint32_t shiftAmountLowerLimit = isShiftRightNarrow ? 1 : 0;
const uint32_t shiftAmountUpperLimit = isShiftRightNarrow ? elementSize : elementSize - 1;
TR_ASSERT_FATAL_WITH_NODE(node, (shiftAmount >= shiftAmountLowerLimit) && (shiftAmount <= shiftAmountUpperLimit), "Illegal shift amount: %d", shiftAmount);

uint32_t imm = isShiftLeft ? (shiftAmount + elementSize) : (elementSize * 2 - shiftAmount);
return generateTrg1Src1ImmInstruction(cg, op, node, treg, sreg, imm, preced);
Expand Down
18 changes: 16 additions & 2 deletions compiler/aarch64/codegen/OMRInstOpCode.enum
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Expand Up @@ -721,8 +721,8 @@
vorrimm4s, /* 0x4F001400, ORR */
/*
* Vector Shift Immediate
* Please do not change or insert opcode between vshl16b and vushr2d.
* Binary Encoder expects vshl16b - vushr2d appears contiguously in this order.
* Please do not change or insert opcode between vshl16b and vsri_2d.
* Binary Encoder expects vshl16b - vsri_2d appears contiguously in this order.
*/
vshl16b, /* 0x4F085400, SHL */
vshl8h, /* 0x4F105400, SHL */
Expand All @@ -740,14 +740,28 @@
vushll2_8h, /* 0x6F08A400, USHLL2 */
vushll2_4s, /* 0x6F10A400, USHLL2 */
vushll2_2d, /* 0x6F20A400, USHLL2 */
vsli16b, /* 0x6F085400, SLI */
vsli8h, /* 0x6F105400, SLI */
vsli4s, /* 0x6F205400, SLI */
vsli2d, /* 0x6F405400, SLI */
vsshr16b, /* 0x4F080400, SSHR */
vsshr8h, /* 0x4F100400, SSHR */
vsshr4s, /* 0x4F200400, SSHR */
vsshr2d, /* 0x4F400400, SSHR */
vshrn_8b, /* 0x0F088400, SHRN */
vshrn_4h, /* 0x0F108400, SHRN */
vshrn_2s, /* 0x0F208400, SHRN */
vshrn2_16b, /* 0x4F088400, SHRN */
vshrn2_8h, /* 0x4F108400, SHRN */
vshrn2_4s, /* 0x4F208400, SHRN */
vushr16b, /* 0x6F080400, USHR */
vushr8h, /* 0x6F100400, USHR */
vushr4s, /* 0x6F200400, USHR */
vushr2d, /* 0x6F400400, USHR */
vsri16b, /* 0x6F084400, SRI */
vsri8h, /* 0x6F104400, SRI */
vsri4s, /* 0x6F204400, SRI */
vsri2d, /* 0x6F404400, SRI */
vshll_8h, /* 0x2E213800, SHLL */
vshll_4s, /* 0x2E613800, SHLL */
vshll_2d, /* 0x2EA13800, SHLL */
Expand Down
14 changes: 14 additions & 0 deletions compiler/aarch64/codegen/OpBinary.cpp
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Expand Up @@ -741,14 +741,28 @@ const OMR::ARM64::InstOpCode::OpCodeBinaryEntry OMR::ARM64::InstOpCode::binaryEn
0x6F08A400, /* USHLL2 vushll2_8h */
0x6F10A400, /* USHLL2 vushll2_4s */
0x6F20A400, /* USHLL2 vushll2_2d */
0x6F085400, /* SLI vsli16b */
0x6F105400, /* SLI vsli8h */
0x6F205400, /* SLI vsli4s */
0x6F405400, /* SLI vsli2d */
0x4F080400, /* SSHR vsshr16b */
0x4F100400, /* SSHR vsshr8h */
0x4F200400, /* SSHR vsshr4s */
0x4F400400, /* SSHR vsshr2d */
0x0F088400, /* SHRN vshrn_8b */
0x0F108400, /* SHRN vshrn_4h */
0x0F208400, /* SHRN vshrn_2s */
0x4F088400, /* SHRN2 vshrn2_16b */
0x4F108400, /* SHRN2 vshrn2_8h */
0x4F208400, /* SHRN2 vshrn2_4s */
0x6F080400, /* USHR vushr16b */
0x6F100400, /* USHR vushr8h */
0x6F200400, /* USHR vushr4s */
0x6F400400, /* USHR vushr2d */
0x6F084400, /* SRI vsri16b */
0x6F104400, /* SRI vsri8h */
0x6F204400, /* SRI vsri4s */
0x6F404400, /* SRI vsri2d */
0x2E213800, /* SHLL vshll_8h */
0x2E613800, /* SHLL vshll_4s */
0x2EA13800, /* SHLL vshll_2d */
Expand Down
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