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regenerated wrappers
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NouranAbdelaziz committed May 9, 2024
1 parent b9a9882 commit 33cdf99
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8 changes: 4 additions & 4 deletions README.md
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Expand Up @@ -141,11 +141,11 @@ RX_FIFO Level Register
### RX_FIFO_THRESHOLD Register [Offset: 0xfe04, mode: w]

RX_FIFO Level Threshold Register
<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>

|bit|field name|width|description|
|---|---|---|---|
|0|threshold|1|FIFO level threshold value|
|0|threshold|4|FIFO level threshold value|


### RX_FIFO_FLUSH Register [Offset: 0xfe08, mode: w]
Expand All @@ -171,11 +171,11 @@ TX_FIFO Level Register
### TX_FIFO_THRESHOLD Register [Offset: 0xfe14, mode: w]

TX_FIFO Level Threshold Register
<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>

|bit|field name|width|description|
|---|---|---|---|
|0|threshold|1|FIFO level threshold value|
|0|threshold|4|FIFO level threshold value|


### TX_FIFO_FLUSH Register [Offset: 0xfe18, mode: w]
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12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
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Expand Up @@ -233,11 +233,11 @@ module EF_UART_AHBL #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
RX_FIFO_THRESHOLD_REG <= HWDATA[1-1:0];
RX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -250,11 +250,11 @@ module EF_UART_AHBL #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
TX_FIFO_THRESHOLD_REG <= HWDATA[1-1:0];
TX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
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12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_AHBL.v
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Original file line number Diff line number Diff line change
Expand Up @@ -125,9 +125,9 @@ module EF_UART_AHBL #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -136,9 +136,9 @@ module EF_UART_AHBL #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
`AHBL_REG(TX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`AHBL_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
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12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -202,11 +202,11 @@ module EF_UART_APB #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
else if(apb_we & (PADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
RX_FIFO_THRESHOLD_REG <= PWDATA[1-1:0];
RX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -219,11 +219,11 @@ module EF_UART_APB #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge PCLK or negedge PRESETn) if(~PRESETn) TX_FIFO_THRESHOLD_REG <= 0;
else if(apb_we & (PADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
TX_FIFO_THRESHOLD_REG <= PWDATA[1-1:0];
TX_FIFO_THRESHOLD_REG <= PWDATA[FAW-1:0];

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
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12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_APB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -125,9 +125,9 @@ module EF_UART_APB #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
`APB_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`APB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -136,9 +136,9 @@ module EF_UART_APB #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
`APB_REG(TX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`APB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
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12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_WB.pp.v
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Original file line number Diff line number Diff line change
Expand Up @@ -189,9 +189,9 @@ module EF_UART_WB #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[1-1:0];
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -200,9 +200,9 @@ module EF_UART_WB #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET)) TX_FIFO_THRESHOLD_REG <= dat_i[1-1:0];
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET)) TX_FIFO_THRESHOLD_REG <= dat_i[FAW-1:0];

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
Expand Down
12 changes: 6 additions & 6 deletions hdl/rtl/bus_wrappers/EF_UART_WB.v
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Original file line number Diff line number Diff line change
Expand Up @@ -125,9 +125,9 @@ module EF_UART_WB #(
wire [FAW-1:0] RX_FIFO_LEVEL_WIRE;
assign RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;

reg [0:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[0 : 0];
`WB_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] RX_FIFO_THRESHOLD_REG;
assign rxfifotr = RX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`WB_REG(RX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] RX_FIFO_FLUSH_REG;
assign rx_fifo_flush = RX_FIFO_FLUSH_REG[0 : 0];
Expand All @@ -136,9 +136,9 @@ module EF_UART_WB #(
wire [FAW-1:0] TX_FIFO_LEVEL_WIRE;
assign TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;

reg [0:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[0 : 0];
`WB_REG(TX_FIFO_THRESHOLD_REG, 0, 1)
reg [FAW-1:0] TX_FIFO_THRESHOLD_REG;
assign txfifotr = TX_FIFO_THRESHOLD_REG[(FAW - 1) : 0];
`WB_REG(TX_FIFO_THRESHOLD_REG, 0, FAW)

reg [0:0] TX_FIFO_FLUSH_REG;
assign tx_fifo_flush = TX_FIFO_FLUSH_REG[0 : 0];
Expand Down

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