Merge pull request #136 from enjoy-digital/gen4_rework

Gen4 rework
enjoy-digital · May 6, 2024 · 3c3c1fc · 3c3c1fc
2 parents 9809d75 + 662b78a
commit 3c3c1fc
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Showing 24 changed files with 9 additions and 14 deletions.
diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py
@@ -411,10 +411,10 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
 
         verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_us")
         platform.add_source(os.path.join(verilog_path, "axis_iff.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{self.nlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{self.nlanes}.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_{self.pcie_data_width}b.v"))
         platform.add_source(os.path.join(verilog_path, "pcie_us_support.v"))
 
     # External Hard IP -----------------------------------------------------------------------------

diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py
@@ -416,14 +416,11 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
 
         verilog_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "xilinx_usp")
         platform.add_source(os.path.join(verilog_path, "axis_iff.v"))
-
-        nvlanes = {"gen3": self.nlanes, "gen4": self.nlanes*2}[self.speed]
-
-        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_x{nvlanes}.v"))
-        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_x{nvlanes}.v"))
-
+
+        platform.add_source(os.path.join(verilog_path, f"s_axis_rq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_rc_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"m_axis_cq_adapt_{self.pcie_data_width}b.v"))
+        platform.add_source(os.path.join(verilog_path, f"s_axis_cc_adapt_{self.pcie_data_width}b.v"))
         platform.add_source(os.path.join(verilog_path, "pcie_usp_support.v"))
 
     # External Hard IP -----------------------------------------------------------------------------

diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v → ...pcie/phy/xilinx_us/m_axis_cq_adapt_128b.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v → ...pcie/phy/xilinx_us/m_axis_cq_adapt_128b.v
diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v → ...pcie/phy/xilinx_us/m_axis_cq_adapt_256b.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v → ...pcie/phy/xilinx_us/m_axis_cq_adapt_256b.v
diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v → ...pcie/phy/xilinx_us/m_axis_rc_adapt_128b.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v → ...pcie/phy/xilinx_us/m_axis_rc_adapt_128b.v
diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v → ...pcie/phy/xilinx_us/m_axis_rc_adapt_256b.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v → ...pcie/phy/xilinx_us/m_axis_rc_adapt_256b.v
diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v → ...pcie/phy/xilinx_us/s_axis_cc_adapt_128b.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v → ...pcie/phy/xilinx_us/s_axis_cc_adapt_128b.v
diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v → ...pcie/phy/xilinx_us/s_axis_cc_adapt_256b.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v → ...pcie/phy/xilinx_us/s_axis_cc_adapt_256b.v
diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v → ...pcie/phy/xilinx_us/s_axis_rq_adapt_128b.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v → ...pcie/phy/xilinx_us/s_axis_rq_adapt_128b.v
diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v → ...pcie/phy/xilinx_us/s_axis_rq_adapt_256b.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v → ...pcie/phy/xilinx_us/s_axis_rq_adapt_256b.v
diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_128b.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x4.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_128b.v
diff --git a/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_256b.v b/litepcie/phy/xilinx_usp/m_axis_cq_adapt_x8.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_256b.v
diff --git a/...pcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_512b.v b/...pcie/phy/xilinx_usp/m_axis_cq_adapt_x16.v → ...cie/phy/xilinx_usp/m_axis_cq_adapt_512b.v
diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_128b.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x4.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_128b.v
diff --git a/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_256b.v b/litepcie/phy/xilinx_usp/m_axis_rc_adapt_x8.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_256b.v
diff --git a/...pcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_512b.v b/...pcie/phy/xilinx_usp/m_axis_rc_adapt_x16.v → ...cie/phy/xilinx_usp/m_axis_rc_adapt_512b.v
diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_128b.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x4.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_128b.v
diff --git a/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_256b.v b/litepcie/phy/xilinx_usp/s_axis_cc_adapt_x8.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_256b.v
diff --git a/...pcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_512b.v b/...pcie/phy/xilinx_usp/s_axis_cc_adapt_x16.v → ...cie/phy/xilinx_usp/s_axis_cc_adapt_512b.v
diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_128b.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x4.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_128b.v
diff --git a/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_256b.v b/litepcie/phy/xilinx_usp/s_axis_rq_adapt_x8.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_256b.v
diff --git a/...pcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_512b.v b/...pcie/phy/xilinx_usp/s_axis_rq_adapt_x16.v → ...cie/phy/xilinx_usp/s_axis_rq_adapt_512b.v
diff --git a/litepcie/software/kernel/liteuart.c b/litepcie/software/kernel/liteuart.c
@@ -3,7 +3,6 @@
  * LiteUART serial controller (LiteX) Driver
  *
  * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
- * Copyright (C) 2024 John Simons <[email protected]>
  */
 
 #include <linux/console.h>

diff --git a/litepcie/tlp/packetizer.py b/litepcie/tlp/packetizer.py
@@ -2,7 +2,6 @@
 # This file is part of LitePCIe.
 #
 # Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
-# Copyright (c) 2024 John Simons <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *