example: uniformize kc705/kcu105 examples.

enjoy-digital · Jun 12, 2020 · 761f8fb · 761f8fb
1 parent c84605e
commit 761f8fb
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Showing 3 changed files with 7 additions and 6 deletions.
diff --git a/examples/kc705.py b/examples/kc705.py
@@ -63,18 +63,19 @@ def __init__(self, platform, nlanes=1):
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
+        self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x" + str(nlanes)),
             data_width = 128,
-            bar0_size  = 0x20000)
+            bar0_size  = 0x20000
+        )
         self.pcie_phy.add_timing_constraints(platform)
         platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
         self.add_csr("pcie_phy")
 
         # Endpoint
         self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy,
-			endianness="big",
-			max_pending_requests=8
-		)
+            endianness           = "big",
+            max_pending_requests = 8
+        )
 
         # Wishbone bridge
         self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint,

diff --git a/examples/kcu105.py b/examples/kcu105.py
@@ -38,7 +38,7 @@ def __init__(self, platform, sys_clk_freq):
         self.sync += If(self.rst.re, rst_delay.wait.eq(1))
 
         # PLL
-        self.submodules.pll = pll = USPLL()
+        self.submodules.pll = pll = USPLL(speedgrade=-2)
         self.comb += pll.reset.eq(rst_delay.done)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)

diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py