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phy/xilinx-7-series: remove qpll1 support
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QPLL1 support is no longer used and removing support allow using un-modified generated files from wrapper.
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@enjoy-digital
enjoy-digital committed Nov 4, 2019
1 parent 0c0519a commit a2fa870
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Showing 11 changed files with 659 additions and 963 deletions.
24 changes: 1 addition & 23 deletions litepcie/phy/s7pciephy.py
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Original file line number Diff line number Diff line change
Expand Up @@ -174,35 +174,13 @@ def convert_size(command, size):

i_cfg_interrupt=cfg_msi.valid,
o_cfg_interrupt_rdy=cfg_msi.ready,
i_cfg_interrupt_di=cfg_msi.dat,

i_QPLL_PLL1PD=1,
i_cfg_interrupt_di=cfg_msi.dat
)
if data_width == 128:
self.comb += m_axis_rx.last.eq(m_axis_rx_tuser[21])
else:
self.comb += m_axis_rx.last.eq(m_axis_rx_tlast)

# Second PLL registration ----------------------------------------------------------------------
def register_pll1(self, pll1):
# The Xilinx's Hard IP integrates the transceivers but also the PLLs. Only one PLL is use
# for PCIe, on some designs having access to the second PLL is needed.
self.pcie_phy_params.update(
p_QPLL_PLL1_FBDIV=pll1.config["n2"],
p_QPLL_PLL1_FBDIV_45=pll1.config["n1"],
p_QPLL_PLL1_REFCLK_DIV=pll1.config["m"],

i_QPLL_GTGREFCLK1=pll1.gtgrefclk,
i_QPLL_GTREFCLK1=pll1.gtrefclk,
i_QPLL_PLL1LOCKEN=1,
i_QPLL_PLL1PD=0,
i_QPLL_PLL1REFCLKSEL=pll1.refclksel,
i_QPLL_PLL1RESET=pll1.reset,
o_QPLL_PLL1LOCK=pll1.lock,
o_QPLL_PLL1OUTCLK=pll1.clk,
o_QPLL_PLL1OUTREFCLK=pll1.refclk
)

# Hard IP sources ------------------------------------------------------------------------------
@staticmethod
def add_sources(platform, phy_path):
Expand Down
40 changes: 6 additions & 34 deletions litepcie/phy/xilinx/7-series/artix7/pcie_core_top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -433,12 +433,7 @@ module pcie_core_top # (
parameter TX_MARGIN_LOW_2 = 7'b1000011,
parameter TX_MARGIN_LOW_3 = 7'b1000010,
parameter TX_MARGIN_LOW_4 = 7'b1000000,
parameter ENABLE_JTAG_DBG = "FALSE",

//---------- QPLL1 Parameters -----------------------
parameter QPLL_PLL1_FBDIV = 4,
parameter QPLL_PLL1_FBDIV_45 = 4,
parameter QPLL_PLL1_REFCLK_DIV = 1
parameter ENABLE_JTAG_DBG = "FALSE"
)
(

Expand Down Expand Up @@ -867,18 +862,7 @@ module pcie_core_top # (

input wire pipe_mmcm_rst_n, // Async | Async
input wire sys_clk,
input wire sys_rst_n,

//---------- QPLL1 Ports ----------------------------
input QPLL_GTGREFCLK1,
input QPLL_GTREFCLK1,
input QPLL_PLL1LOCKEN,
input QPLL_PLL1PD,
input [ 2:0] QPLL_PLL1REFCLKSEL,
input QPLL_PLL1RESET,
output QPLL_PLL1LOCK,
output QPLL_PLL1OUTCLK,
output QPLL_PLL1OUTREFCLK
input wire sys_rst_n
);

wire user_clk;
Expand Down Expand Up @@ -1855,10 +1839,7 @@ pcie_gt_top #(
.TX_MARGIN_LOW_2 ( TX_MARGIN_LOW_2 ),
.TX_MARGIN_LOW_3 ( TX_MARGIN_LOW_3 ),
.TX_MARGIN_LOW_4 ( TX_MARGIN_LOW_4 ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND ),
.QPLL_PLL1_FBDIV (QPLL_PLL1_FBDIV),
.QPLL_PLL1_FBDIV_45 (QPLL_PLL1_FBDIV_45),
.QPLL_PLL1_REFCLK_DIV (QPLL_PLL1_REFCLK_DIV)
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )

) gt_top_i (
// pl ltssm
Expand Down Expand Up @@ -2124,18 +2105,7 @@ pcie_gt_top #(
.PIPE_DEBUG_7 ( pipe_debug_7 ),
.PIPE_DEBUG_8 ( pipe_debug_8 ),
.PIPE_DEBUG_9 ( pipe_debug_9 ),
.PIPE_DEBUG ( pipe_debug ),

//---------- QPLL1 Ports ----------------
.QPLL_GTGREFCLK1 (QPLL_GTGREFCLK1),
.QPLL_GTREFCLK1 (QPLL_GTREFCLK1),
.QPLL_PLL1LOCKEN (QPLL_PLL1LOCKEN),
.QPLL_PLL1PD (QPLL_PLL1PD),
.QPLL_PLL1REFCLKSEL (QPLL_PLL1REFCLKSEL),
.QPLL_PLL1RESET (QPLL_PLL1RESET),
.QPLL_PLL1LOCK (QPLL_PLL1LOCK),
.QPLL_PLL1OUTCLK (QPLL_PLL1OUTCLK),
.QPLL_PLL1OUTREFCLK (QPLL_PLL1OUTREFCLK)
.PIPE_DEBUG ( pipe_debug )
);

assign common_commands_out = 12'b0;
Expand Down Expand Up @@ -2176,4 +2146,6 @@ pcie_gt_top #(
//enable_jtag_dbg = FALSE




endmodule
51 changes: 8 additions & 43 deletions litepcie/phy/xilinx/7-series/common/pcie.v
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
Expand Down Expand Up @@ -40,10 +40,10 @@
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
// DO NOT MODIFY THIS FILE.


Expand All @@ -64,10 +64,7 @@ _control_encodedbar3=00,c_rbar_cap_sup4=00001,c_rbar_cap_index4=0,c_rbar_cap_con
TATUS_PORTS=FALSE,SHARED_LOGIC_IN_CORE=FALSE,ERR_REPORTING_IF=TRUE,PL_INTERFACE=TRUE,CFG_MGMT_IF=TRUE,CFG_CTL_IF=TRUE,CFG_STATUS_IF=TRUE,RCV_MSG_IF=TRUE,CFG_FC_IF=TRUE,EXT_PIPE_INTERFACE=FALSE,EXT_STARTUP_PRIMITIVE=FALSE,KEEP_WIDTH=8,PCIE_ASYNC_EN=FALSE,ENABLE_JTAG_DBG=FALSE}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie # (
parameter C_BAR0 = 32'hF0000000,
parameter QPLL_PLL1_FBDIV = 4,
parameter QPLL_PLL1_FBDIV_45 = 4,
parameter QPLL_PLL1_REFCLK_DIV = 1
parameter C_BAR0 = 32'hF0000000
)(
pci_exp_txp,
pci_exp_txn,
Expand Down Expand Up @@ -244,16 +241,7 @@ module pcie # (
pcie_drp_addr,
pcie_drp_di,
pcie_drp_do,
pcie_drp_rdy,
QPLL_GTGREFCLK1,
QPLL_GTREFCLK1,
QPLL_PLL1LOCKEN,
QPLL_PLL1PD,
QPLL_PLL1REFCLKSEL,
QPLL_PLL1RESET,
QPLL_PLL1LOCK,
QPLL_PLL1OUTCLK,
QPLL_PLL1OUTREFCLK
pcie_drp_rdy
);

(* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp" *)
Expand Down Expand Up @@ -612,16 +600,6 @@ output wire [15 : 0] pcie_drp_do;
(* X_INTERFACE_INFO = "xilinx.com:interface:drp:1.0 drp DRDY" *)
output wire pcie_drp_rdy;

input QPLL_GTGREFCLK1;
input QPLL_GTREFCLK1;
input QPLL_PLL1LOCKEN;
input QPLL_PLL1PD;
input [ 2:0] QPLL_PLL1REFCLKSEL;
input QPLL_PLL1RESET;
output QPLL_PLL1LOCK;
output QPLL_PLL1OUTCLK;
output QPLL_PLL1OUTREFCLK;

pcie_pcie2_top #(
.c_component_name("pcie"),
.dev_port_type("0000"),
Expand Down Expand Up @@ -834,10 +812,7 @@ output QPLL_PLL1OUTREFCLK;
.EXT_STARTUP_PRIMITIVE("FALSE"),
.KEEP_WIDTH(8),
.PCIE_ASYNC_EN("FALSE"),
.ENABLE_JTAG_DBG("FALSE"),
.QPLL_PLL1_FBDIV (QPLL_PLL1_FBDIV),
.QPLL_PLL1_FBDIV_45 (QPLL_PLL1_FBDIV_45),
.QPLL_PLL1_REFCLK_DIV (QPLL_PLL1_REFCLK_DIV)
.ENABLE_JTAG_DBG("FALSE")
) inst (
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),
Expand Down Expand Up @@ -1128,16 +1103,6 @@ output QPLL_PLL1OUTREFCLK;
.pipe_tx_4_sigs(),
.pipe_tx_5_sigs(),
.pipe_tx_6_sigs(),
.pipe_tx_7_sigs(),
//---------- QPLL1 Ports ----------------
.QPLL_GTGREFCLK1 (QPLL_GTGREFCLK1),
.QPLL_GTREFCLK1 (QPLL_GTREFCLK1),
.QPLL_PLL1LOCKEN (QPLL_PLL1LOCKEN),
.QPLL_PLL1PD (QPLL_PLL1PD),
.QPLL_PLL1REFCLKSEL (QPLL_PLL1REFCLKSEL),
.QPLL_PLL1RESET (QPLL_PLL1RESET),
.QPLL_PLL1LOCK (QPLL_PLL1LOCK),
.QPLL_PLL1OUTCLK (QPLL_PLL1OUTCLK),
.QPLL_PLL1OUTREFCLK (QPLL_PLL1OUTREFCLK)
.pipe_tx_7_sigs()
);
endmodule
44 changes: 7 additions & 37 deletions litepcie/phy/xilinx/7-series/common/pcie_gt_common.v
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Original file line number Diff line number Diff line change
Expand Up @@ -59,12 +59,7 @@ parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "2.1", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency

//---------- QPLL1 Parameters -----------------------
parameter QPLL_PLL1_FBDIV = 4,
parameter QPLL_PLL1_FBDIV_45 = 4,
parameter QPLL_PLL1_REFCLK_DIV = 1
parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency
)

(
Expand All @@ -77,24 +72,13 @@ input QPLL_DRP_RST_N,
input QPLL_DRP_OVRD,
input QPLL_DRP_GEN3,
input QPLL_DRP_START,
output [5:0] QPLL_DRP_CRSCODE,
output [8:0] QPLL_DRP_FSM,
output [5:0] QPLL_DRP_CRSCODE,
output [8:0] QPLL_DRP_FSM,
output QPLL_DRP_DONE,
output QPLL_DRP_RESET,
output QPLL_QPLLLOCK,
output QPLL_QPLLOUTCLK,
output QPLL_QPLLOUTREFCLK,

//---------- QPLL1 Ports ---------------------------
input QPLL_GTGREFCLK1,
input QPLL_GTREFCLK1,
input QPLL_PLL1LOCKEN,
input QPLL_PLL1PD,
input [ 2:0] QPLL_PLL1REFCLKSEL,
input QPLL_PLL1RESET,
output QPLL_PLL1LOCK,
output QPLL_PLL1OUTCLK,
output QPLL_PLL1OUTREFCLK
output QPLL_QPLLOUTREFCLK
);

//---------- QPLL DRP Module Output --------------------
Expand Down Expand Up @@ -155,10 +139,7 @@ pcie_qpll_wrapper #
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.QPLL_PLL1_FBDIV (QPLL_PLL1_FBDIV),
.QPLL_PLL1_FBDIV_45 (QPLL_PLL1_FBDIV_45),
.QPLL_PLL1_REFCLK_DIV (QPLL_PLL1_REFCLK_DIV)
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
qpll_wrapper_i
(
Expand All @@ -179,18 +160,7 @@ pcie_qpll_wrapper #
.QPLL_DRPDI (qpll_drp_di),
.QPLL_DRPWE (qpll_drp_we),
.QPLL_DRPDO (qpll_drp_do),
.QPLL_DRPRDY (qpll_drp_rdy),

//---------- QPLL1 Ports ----------------
.QPLL_GTGREFCLK1 (QPLL_GTGREFCLK1),
.QPLL_GTREFCLK1 (QPLL_GTREFCLK1),
.QPLL_PLL1LOCKEN (QPLL_PLL1LOCKEN),
.QPLL_PLL1PD (QPLL_PLL1PD),
.QPLL_PLL1REFCLKSEL (QPLL_PLL1REFCLKSEL),
.QPLL_PLL1RESET (QPLL_PLL1RESET),
.QPLL_PLL1LOCK (QPLL_PLL1LOCK),
.QPLL_PLL1OUTCLK (QPLL_PLL1OUTCLK),
.QPLL_PLL1OUTREFCLK (QPLL_PLL1OUTREFCLK)
.QPLL_DRPRDY (qpll_drp_rdy)
);

endmodule
37 changes: 4 additions & 33 deletions litepcie/phy/xilinx/7-series/common/pcie_gt_top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -87,12 +87,7 @@ module pcie_gt_top #
parameter TX_MARGIN_LOW_4 = 7'b1000000,

parameter PCIE_CHAN_BOND = 0,
parameter TCQ = 1, //synthesis warning solved: parameter declaration becomes local

//---------- QPLL1 Parameters -----------------------
parameter QPLL_PLL1_FBDIV = 4,
parameter QPLL_PLL1_FBDIV_45 = 4,
parameter QPLL_PLL1_REFCLK_DIV = 1
parameter TCQ = 1 //synthesis warning solved: parameter declaration becomes local
)
(
//-----------------------------------------------------------------------------------------------------------------//
Expand Down Expand Up @@ -354,18 +349,7 @@ module pcie_gt_top #
output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0]ext_ch_gt_drpdo,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,

output wire phy_rdy_n,

//---------- QPLL1 Ports ----------------------------
input QPLL_GTGREFCLK1,
input QPLL_GTREFCLK1,
input QPLL_PLL1LOCKEN,
input QPLL_PLL1PD,
input [ 2:0] QPLL_PLL1REFCLKSEL,
input QPLL_PLL1RESET,
output QPLL_PLL1LOCK,
output QPLL_PLL1OUTCLK,
output QPLL_PLL1OUTREFCLK
output wire phy_rdy_n
);


Expand Down Expand Up @@ -502,10 +486,7 @@ pcie_pipe_wrapper #
.PCIE_OOBCLK_MODE ( PCIE_OOBCLK_MODE_ENABLE ),
.PCIE_REFCLK_FREQ ( REF_CLK_FREQ ),
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ),
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ),
.QPLL_PLL1_FBDIV (QPLL_PLL1_FBDIV),
.QPLL_PLL1_FBDIV_45 (QPLL_PLL1_FBDIV_45),
.QPLL_PLL1_REFCLK_DIV (QPLL_PLL1_REFCLK_DIV)
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 )

) pipe_wrapper_i (

Expand Down Expand Up @@ -690,17 +671,7 @@ pcie_pipe_wrapper #
.PIPE_DEBUG_8 ( PIPE_DEBUG_8 ),
.PIPE_DEBUG_9 ( PIPE_DEBUG_9 ),
.PIPE_DEBUG ( PIPE_DEBUG ),
.PIPE_DMONITOROUT ( PIPE_DMONITOROUT ),
//---------- QPLL1 Ports ----------------
.QPLL_GTGREFCLK1 (QPLL_GTGREFCLK1),
.QPLL_GTREFCLK1 (QPLL_GTREFCLK1),
.QPLL_PLL1LOCKEN (QPLL_PLL1LOCKEN),
.QPLL_PLL1PD (QPLL_PLL1PD),
.QPLL_PLL1REFCLKSEL (QPLL_PLL1REFCLKSEL),
.QPLL_PLL1RESET (QPLL_PLL1RESET),
.QPLL_PLL1LOCK (QPLL_PLL1LOCK),
.QPLL_PLL1OUTCLK (QPLL_PLL1OUTCLK),
.QPLL_PLL1OUTREFCLK (QPLL_PLL1OUTREFCLK)
.PIPE_DMONITOROUT ( PIPE_DMONITOROUT )
);

assign PIPE_RXSTATUS = gt_rx_status_wire_filter;
Expand Down
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