global: Minor cleanup/update.

enjoy-digital · Nov 17, 2023 · fdca75a · fdca75a
1 parent 526a3d0
commit fdca75a
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Showing 13 changed files with 70 additions and 56 deletions.
diff --git a/litepcie/common.py b/litepcie/common.py
@@ -1,7 +1,7 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2018 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *

diff --git a/litepcie/core/common.py b/litepcie/core/common.py
@@ -1,11 +1,13 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2022 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
+from litex.gen import *
+
 from litepcie.common import *
 
 # LitePCIe Internal Ports --------------------------------------------------------------------------

diff --git a/litepcie/core/crossbar.py b/litepcie/core/crossbar.py
@@ -1,18 +1,20 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2022 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
-from litepcie.common import *
-from litepcie.core.common import *
+from litex.gen import *
+
+from litepcie.common         import *
+from litepcie.core.common    import *
 from litepcie.tlp.controller import LitePCIeTLPController
 
 # LitePCIe Crossbar --------------------------------------------------------------------------------
 
-class LitePCIeCrossbar(Module):
+class LitePCIeCrossbar(LiteXModule):
     def __init__(self, data_width, address_width, max_pending_requests, cmp_bufs_buffered=True):
         self.data_width           = data_width
         self.address_width        = address_width

diff --git a/litepcie/core/endpoint.py b/litepcie/core/endpoint.py
@@ -11,8 +11,8 @@
 from litex.soc.interconnect.csr import *
 
 from litepcie.tlp.depacketizer import LitePCIeTLPDepacketizer
-from litepcie.tlp.packetizer import LitePCIeTLPPacketizer
-from litepcie.core.crossbar import LitePCIeCrossbar
+from litepcie.tlp.packetizer   import LitePCIeTLPPacketizer
+from litepcie.core.crossbar    import LitePCIeCrossbar
 
 # LitePCIe Endpoint --------------------------------------------------------------------------------
 

diff --git a/litepcie/core/msi.py b/litepcie/core/msi.py
@@ -1,19 +1,21 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2022 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
-from litex.soc.interconnect.csr import *
+from litex.gen import *
+
+from litex.soc.interconnect.csr     import *
 from litex.soc.interconnect.csr_bus import SRAM
 
 from litepcie.common import *
 
 # LitePCIeMSI --------------------------------------------------------------------------------------
 
-class LitePCIeMSI(Module, AutoCSR):
+class LitePCIeMSI(LiteXModule):
     def __init__(self, width=32):
         self.irqs   = Signal(width)
         self.source = stream.Endpoint(msi_layout())
@@ -49,7 +51,7 @@ def __init__(self, width=32):
 
 # LitePCIeMSIMultiVector ---------------------------------------------------------------------------
 
-class LitePCIeMSIMultiVector(Module, AutoCSR):
+class LitePCIeMSIMultiVector(LiteXModule):
   def __init__(self, width=32):
         self.irqs   = Signal(width)
         self.source = stream.Endpoint(msi_layout())
@@ -81,7 +83,7 @@ def __init__(self, width=32):
 
 # LitePCIeMSIX -------------------------------------------------------------------------------------
 
-class LitePCIeMSIX(Module, AutoCSR):
+class LitePCIeMSIX(LiteXModule):
     def __init__(self, endpoint, width=32):
         assert width <= 64
         self.irqs           = Signal(width)
@@ -126,7 +128,7 @@ def __init__(self, endpoint, width=32):
         self.table_port = table_port = self.table.get_port(has_re=True)
         self.specials += table_port
 
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             table_port.adr.eq(msix_num),
             table_port.re.eq(1),

diff --git a/litepcie/frontend/axi.py b/litepcie/frontend/axi.py
@@ -6,15 +6,16 @@
 
 from migen import *
 
-from litex.soc.interconnect import axi, stream
+from litex.gen import *
 
-from litepcie.common import *
+from litex.soc.interconnect import axi, stream
 
+from litepcie.common       import *
 from litepcie.frontend.dma import descriptor_layout, LitePCIeDMAWriter, LitePCIeDMAReader
 
 # LitePCIeAXISlave ---------------------------------------------------------------------------------
 
-class LitePCIeAXISlave(Module):
+class LitePCIeAXISlave(LiteXModule):
     def __init__(self, endpoint, data_width=32, id_width=1):
         self.axi = axi.AXIInterface(data_width=data_width, id_width=id_width)
 
@@ -33,12 +34,12 @@ def __init__(self, endpoint, data_width=32, id_width=1):
         # AXI Write Path ---------------------------------------------------------------------------
 
         # DMA / FIFO / Converter
-        self.submodules.dma_wr = dma_wr = LitePCIeDMAWriter(
+        self.dma_wr = dma_wr = LitePCIeDMAWriter(
             endpoint = endpoint,
             port     = port_wr,
             with_table = False)
-        self.submodules.fifo_wr = fifo_wr = stream.SyncFIFO(descriptor_layout(), 16)
-        self.submodules.conv_wr = conv_wr = stream.Converter(nbits_from=data_width, nbits_to=endpoint.phy.data_width)
+        self.fifo_wr = fifo_wr = stream.SyncFIFO(descriptor_layout(), 16)
+        self.conv_wr = conv_wr = stream.Converter(nbits_from=data_width, nbits_to=endpoint.phy.data_width)
 
         # Flow
         self.comb += [
@@ -51,7 +52,7 @@ def __init__(self, endpoint, data_width=32, id_width=1):
         self.comb += desc_wr.address.eq(self.axi.aw.addr)                       # Start address (byte addressed)
         self.comb += desc_wr.length.eq((self.axi.aw.len + 1) * (data_width//8)) # Transfer length (in bytes)
 
-        self.submodules.fsm_wr = fsm_wr = FSM(reset_state="WRITE-IDLE")
+        self.fsm_wr = fsm_wr = FSM(reset_state="WRITE-IDLE")
         fsm_wr.act("WRITE-IDLE",
             self.axi.aw.ready.eq(desc_wr.ready),
             desc_wr.valid.eq(self.axi.aw.valid),
@@ -87,12 +88,12 @@ def __init__(self, endpoint, data_width=32, id_width=1):
         # AXI Read Path ----------------------------------------------------------------------------
 
         # DMA / FIFO / Converter
-        self.submodules.dma_rd = dma_rd = LitePCIeDMAReader(
+        self.dma_rd = dma_rd = LitePCIeDMAReader(
             endpoint = endpoint,
             port     = port_rd,
             with_table = False)
-        self.submodules.fifo_rd = fifo_rd = stream.SyncFIFO(descriptor_layout(), 16)
-        self.submodules.conv_rd = conv_rd = stream.Converter(nbits_from=endpoint.phy.data_width, nbits_to=data_width)
+        self.fifo_rd = fifo_rd = stream.SyncFIFO(descriptor_layout(), 16)
+        self.conv_rd = conv_rd = stream.Converter(nbits_from=endpoint.phy.data_width, nbits_to=data_width)
 
         # Flow
         self.comb += [
@@ -105,7 +106,7 @@ def __init__(self, endpoint, data_width=32, id_width=1):
         self.comb += desc_rd.address.eq(self.axi.ar.addr)                       # Starting address (byte addressed)
         self.comb += desc_rd.length.eq((self.axi.ar.len + 1) * (data_width//8)) # Transfer length (in bytes)
 
-        self.submodules.fsm_rd = fsm_rd = FSM(reset_state="READ-IDLE")
+        self.fsm_rd = fsm_rd = FSM(reset_state="READ-IDLE")
         fsm_rd.act("READ-IDLE",
             self.axi.ar.ready.eq(desc_rd.ready),
             desc_rd.valid.eq(self.axi.ar.valid),

diff --git a/litepcie/frontend/dma.py b/litepcie/frontend/dma.py
@@ -9,10 +9,10 @@
 
 from litex.gen import *
 
-from litex.soc.interconnect import stream
+from litex.soc.interconnect     import stream
 from litex.soc.interconnect.csr import *
 
-from litepcie.common import *
+from litepcie.common     import *
 from litepcie.tlp.common import *
 
 # Constants/Layouts --------------------------------------------------------------------------------

diff --git a/litepcie/frontend/ptm/core.py b/litepcie/frontend/ptm/core.py
@@ -10,7 +10,7 @@
 from litex.gen import *
 from litex.gen.genlib.misc import WaitTimer
 
-from litex.soc.interconnect.csr import *
+from litex.soc.interconnect.csr    import *
 from litex.soc.interconnect import stream
 
 from litepcie.common import phy_layout

diff --git a/litepcie/frontend/ptm/sniffer.py b/litepcie/frontend/ptm/sniffer.py
@@ -13,7 +13,7 @@
 
 from litex.soc.interconnect import stream
 
-from litepcie.common import phy_layout
+from litepcie.common     import phy_layout
 from litepcie.tlp.common import fmt_type_dict
 
 from litepcie.tlp.depacketizer import LitePCIeTLPDepacketizer

diff --git a/litepcie/frontend/wishbone.py b/litepcie/frontend/wishbone.py
@@ -1,11 +1,13 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2020 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.interconnect import wishbone
 
 from litepcie.common import *
@@ -27,7 +29,7 @@ def map_wishbone_dat(address, data, wishbone_dat, qword_aligned=False):
 
 # LitePCIeWishboneMaster ---------------------------------------------------------------------------
 
-class LitePCIeWishboneMaster(Module):
+class LitePCIeWishboneMaster(LiteXModule):
     def __init__(self, endpoint,
         address_decoder = lambda a: 1,
         base_address    = 0x00000000,
@@ -36,9 +38,11 @@ def __init__(self, endpoint,
 
         # # #
 
+        # Get Slave port from Crossbar.
         port = endpoint.crossbar.get_slave_port(address_decoder)
 
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        # Wishbone Master FSM.
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             If(port.sink.valid & port.sink.first,
                 If(port.sink.we,
@@ -110,9 +114,11 @@ def __init__(self, endpoint, qword_aligned=False):
 
         # # #
 
+        # Get Master port from Crossbar.
         port = endpoint.crossbar.get_master_port()
 
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        # Wishbone Slave FSM.
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             If(self.wishbone.stb & self.wishbone.cyc,
                 If(self.wishbone.we,

diff --git a/litepcie/gen.py b/litepcie/gen.py
@@ -35,25 +35,27 @@
 
 from litex.gen import *
 
-from litex.soc.cores.clock import *
-from litex.soc.interconnect.csr import *
-from litex.soc.interconnect import wishbone
-from litex.soc.interconnect.axi import *
-from litex.soc.integration.soc import SoCRegion
+from litex.soc.cores.clock          import *
+from litex.soc.interconnect.csr     import *
+from litex.soc.interconnect         import wishbone
+from litex.soc.interconnect.axi     import *
+from litex.soc.integration.soc      import SoCRegion
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.builder import *
+from litex.soc.integration.builder  import *
 
-from litepcie.phy.c5pciephy import C5PCIEPHY
-from litepcie.phy.s7pciephy import S7PCIEPHY
-from litepcie.phy.uspciephy import USPCIEPHY
+from litepcie.phy.c5pciephy  import C5PCIEPHY
+from litepcie.phy.s7pciephy  import S7PCIEPHY
+from litepcie.phy.uspciephy  import USPCIEPHY
 from litepcie.phy.usppciephy import USPPCIEPHY
 
 from litepcie.core import LitePCIeEndpoint, LitePCIeMSI, LitePCIeMSIMultiVector, LitePCIeMSIX
-from litepcie.frontend.dma import LitePCIeDMA
+
+from litepcie.frontend.dma      import LitePCIeDMA
 from litepcie.frontend.wishbone import LitePCIeWishboneMaster, LitePCIeWishboneSlave
-from litepcie.frontend.axi import LitePCIeAXISlave
-from litepcie.frontend.ptm import PCIePTMSniffer
-from litepcie.frontend.ptm import PTMCapabilities, PTMRequester
+from litepcie.frontend.axi      import LitePCIeAXISlave
+from litepcie.frontend.ptm      import PCIePTMSniffer
+from litepcie.frontend.ptm      import PTMCapabilities, PTMRequester
+
 from litepcie.software import generate_litepcie_software_headers
 
 from litex.build.generic_platform import *

diff --git a/litepcie/tlp/controller.py b/litepcie/tlp/controller.py
@@ -1,16 +1,16 @@
 #
 # This file is part of LitePCIe.
 #
-# Copyright (c) 2015-2021 Florent Kermarrec <[email protected]>
+# Copyright (c) 2015-2023 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
 from migen import *
 
 from litex.gen import *
 
-from litepcie.common import *
+from litepcie.common      import *
 from litepcie.core.common import *
-from litepcie.tlp.common import *
+from litepcie.tlp.common  import *
 
 # LitePCIe TLP Controller --------------------------------------------------------------------------
 

diff --git a/litepcie/tlp/packetizer.py b/litepcie/tlp/packetizer.py
@@ -7,7 +7,6 @@
 from migen import *
 
 from litex.gen import *
-from litex.gen.genlib.misc import chooser
 
 from litepcie.tlp.common import *
 
@@ -933,12 +932,12 @@ def __init__(self, data_width, endianness, address_width=32, capabilities=["REQU
                 tlp_ptm.first.eq(ptm_sink.first),
                 tlp_ptm.last.eq(ptm_sink.last),
 
-                tlp_ptm.tc.eq(0),   # CHECKME.
-                tlp_ptm.ln.eq(0),   # CHECKME.
-                tlp_ptm.th.eq(0),   # CHECKME.
-                tlp_ptm.td.eq(0),   # CHECKME.
-                tlp_ptm.ep.eq(0),   # CHECKME.
-                tlp_ptm.attr.eq(0), # CHECKME.
+                tlp_ptm.tc.eq(0),
+                tlp_ptm.ln.eq(0),
+                tlp_ptm.th.eq(0),
+                tlp_ptm.td.eq(0),
+                tlp_ptm.ep.eq(0),
+                tlp_ptm.attr.eq(0),
                 tlp_ptm.length.eq(ptm_sink.length),
 
                 tlp_ptm.requester_id.eq(ptm_sink.requester_id),