Add support for ESP32-P4 (#47)

* Add initial support for ESP32-P4 (no halting, yet)

* Check `esp32p4` feature in CI

.github/workflows/ci.yml

@@ -18,7 +18,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        chip: [esp32c2, esp32c3, esp32c6, esp32h2]
+        chip: [esp32c2, esp32c3, esp32c6, esp32h2, esp32p4]
         printer: ["esp-println/uart"]
     steps:
       - uses: actions/checkout@v3

Cargo.toml

@@ -23,6 +23,7 @@ esp32c2 = ["esp-println?/esp32c2"]
 esp32c3 = ["esp-println?/esp32c3"]
 esp32c6 = ["esp-println?/esp32c6"]
 esp32h2 = ["esp-println?/esp32h2"]
+esp32p4 = ["esp-println?/esp32p4"]
 esp32s2 = ["esp-println?/esp32s2"]
 esp32s3 = ["esp-println?/esp32s3"]
 
@@ -38,3 +39,6 @@ exception-handler = []
 panic-handler = []
 halt-cores = []
 colors = []
+
+[patch.crates-io]
+esp-println = { git = "https://github.com/esp-rs/esp-println/", rev = "1f628e3" }

README.md

@@ -1,6 +1,6 @@
 # esp-backtrace - backtrace for ESP32 bare-metal
 
-Supports the ESP32, ESP32-C2/C3/C6, ESP32-S2/S3 and ESP32H2. Optional exception and panic handlers are included, both of which can be enabled via their respective features.
+Supports the ESP32, ESP32-C2/C3/C6, ESP32-H2, ESP32-P4, and ESP32-S2/S3. Optional exception and panic handlers are included, both of which can be enabled via their respective features.
 
 Please note that when targeting a RISC-V device, you **need** to force frame pointers (i.e. `"-C", "force-frame-pointers",` in your `.cargo/config.toml`); this is **not** required for Xtensa.
 
@@ -17,9 +17,10 @@ When using the panic and/or exception handler make sure to include `use esp_back
 | esp32c2           | Target ESP32-C2                                                      |
 | esp32c3           | Target ESP32-C3                                                      |
 | esp32c6           | Target ESP32-C6                                                      |
+| esp32h2           | Target ESP32-H2                                                      |
+| esp32p4           | Target ESP32-P4                                                      |
 | esp32s2           | Target ESP32-S2                                                      |
 | esp32s3           | Target ESP32-S3                                                      |
-| esp32h2           | Target ESP32-H2                                                      |
 | panic-handler     | Include a panic handler, will add `esp-println` as a dependency      |
 | exception-handler | Include an exception handler, will add `esp-println` as a dependency |
 | println           | Use `esp-println` to print messages                                  |

build.rs

@@ -5,9 +5,10 @@ fn main() {
         cfg!(feature = "esp32c2"),
         cfg!(feature = "esp32c3"),
         cfg!(feature = "esp32c6"),
+        cfg!(feature = "esp32h2"),
+        cfg!(feature = "esp32p4"),
         cfg!(feature = "esp32s2"),
         cfg!(feature = "esp32s3"),
-        cfg!(feature = "esp32h2"),
     ];
 
     match chip_features.iter().filter(|&&f| f).count() {

src/lib.rs

@@ -226,6 +226,16 @@ fn is_valid_ram_address(address: u32) -> bool {
         return false;
     }
 
+    #[cfg(feature = "esp32h2")]
+    if !(0x4080_0000..=0x4085_0000).contains(&address) {
+        return false;
+    }
+
+    #[cfg(feature = "esp32p4")]
+    if !(0x4FF0_0000..=0x4FFC_0000).contains(&address) {
+        return false;
+    }
+
     #[cfg(feature = "esp32s2")]
     if !(0x3FFB_0000..=0x4000_0000).contains(&address) {
         return false;
@@ -236,48 +246,60 @@ fn is_valid_ram_address(address: u32) -> bool {
         return false;
     }
 
-    #[cfg(feature = "esp32h2")]
-    if !(0x4080_0000..=0x4085_0000).contains(&address) {
-        return false;
-    }
-
     true
 }
 
 #[cfg(any(
-    not(any(feature = "esp32", feature = "esp32s3")),
+    not(any(feature = "esp32", feature = "esp32p4", feature = "esp32s3")),
     not(feature = "halt-cores")
 ))]
 #[allow(unused)]
 fn halt() -> ! {
     loop {}
 }
 
+// TODO: Enable `halt` function for `esp32p4` feature once implemented
 #[cfg(all(any(feature = "esp32", feature = "esp32s3"), feature = "halt-cores"))]
 #[allow(unused)]
 fn halt() -> ! {
     #[cfg(feature = "esp32")]
     mod registers {
-        pub(crate) const SW_CPU_STALL: u32 = 0x3ff480ac;
         pub(crate) const OPTIONS0: u32 = 0x3ff48000;
+        pub(crate) const SW_CPU_STALL: u32 = 0x3ff480ac;
+    }
+
+    #[cfg(feature = "esp32p4")]
+    mod registers {
+        pub(crate) const SW_CPU_STALL: u32 = 0x50115200;
     }
 
     #[cfg(feature = "esp32s3")]
     mod registers {
-        pub(crate) const SW_CPU_STALL: u32 = 0x600080bc;
         pub(crate) const OPTIONS0: u32 = 0x60008000;
+        pub(crate) const SW_CPU_STALL: u32 = 0x600080bc;
     }
 
     let sw_cpu_stall = registers::SW_CPU_STALL as *mut u32;
-    let options0 = registers::OPTIONS0 as *mut u32;
 
+    #[cfg(feature = "esp32p4")]
+    unsafe {}
+
+    #[cfg(not(feature = "esp32p4"))]
     unsafe {
+        // We need to write the value "0x86" to stall a particular core. The write
+        // location is split into two separate bit fields named "c0" and "c1", and the
+        // two fields are located in different registers. Each core has its own pair of
+        // "c0" and "c1" bit fields.
+
+        let options0 = registers::OPTIONS0 as *mut u32;
+
+        options0.write_volatile(options0.read_volatile() & !(0b1111) | 0b1010);
+
         sw_cpu_stall.write_volatile(
             sw_cpu_stall.read_volatile() & !(0b111111 << 20) & !(0b111111 << 26)
                 | (0x21 << 20)
                 | (0x21 << 26),
         );
-        options0.write_volatile(options0.read_volatile() & !(0b1111) | 0b1010);
     }
 
     loop {}