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Add and use TrapFrame::new() in esp-wifi
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bugadani committed Aug 29, 2024
1 parent 6c6cc9b commit 1b17ea0
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Showing 5 changed files with 30 additions and 93 deletions.
2 changes: 2 additions & 0 deletions esp-riscv-rt/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

### Added

Added `TrapFrame::new` (#2038)

### Changed

### Fixed
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13 changes: 13 additions & 0 deletions esp-riscv-rt/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -160,6 +160,19 @@ pub struct TrapFrame {
pub mtval: usize,
}

impl Default for TrapFrame {
fn default() -> Self {
Self::new()
}
}

impl TrapFrame {
/// Creates a new, zeroed out trap frame.
pub const fn new() -> Self {
unsafe { core::mem::zeroed() }
}
}

/// Trap entry point rust (_start_trap_rust)
///
/// `scause`/`mcause` is read to determine the cause of the trap. XLEN-1 bit
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38 changes: 1 addition & 37 deletions esp-wifi/src/preempt/preempt_riscv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -10,43 +10,7 @@ pub struct Context {
}

static mut CTX_TASKS: [Context; MAX_TASK] = [Context {
trap_frame: TrapFrame {
ra: 0,
t0: 0,
t1: 0,
t2: 0,
t3: 0,
t4: 0,
t5: 0,
t6: 0,
a0: 0,
a1: 0,
a2: 0,
a3: 0,
a4: 0,
a5: 0,
a6: 0,
a7: 0,
s0: 0,
s1: 0,
s2: 0,
s3: 0,
s4: 0,
s5: 0,
s6: 0,
s7: 0,
s8: 0,
s9: 0,
s10: 0,
s11: 0,
gp: 0,
tp: 0,
sp: 0,
pc: 0,
mstatus: 0,
mcause: 0,
mtval: 0,
},
trap_frame: TrapFrame::new(),
_running: false,
}; MAX_TASK];

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57 changes: 1 addition & 56 deletions esp-wifi/src/preempt/preempt_xtensa.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,62 +9,7 @@ pub struct TaskContext {
}

static mut CTX_TASKS: [TaskContext; MAX_TASK] = [TaskContext {
trap_frame: TrapFrame {
PC: 0,
PS: 0,
A0: 0,
A1: 0,
A2: 0,
A3: 0,
A4: 0,
A5: 0,
A6: 0,
A7: 0,
A8: 0,
A9: 0,
A10: 0,
A11: 0,
A12: 0,
A13: 0,
A14: 0,
A15: 0,
SAR: 0,
EXCCAUSE: 0,
EXCVADDR: 0,
LBEG: 0,
LEND: 0,
LCOUNT: 0,
THREADPTR: 0,
SCOMPARE1: 0,
BR: 0,
ACCLO: 0,
ACCHI: 0,
M0: 0,
M1: 0,
M2: 0,
M3: 0,
F64R_LO: 0,
F64R_HI: 0,
F64S: 0,
FCR: 0,
FSR: 0,
F0: 0,
F1: 0,
F2: 0,
F3: 0,
F4: 0,
F5: 0,
F6: 0,
F7: 0,
F8: 0,
F9: 0,
F10: 0,
F11: 0,
F12: 0,
F13: 0,
F14: 0,
F15: 0,
},
trap_frame: TrapFrame::new(),
}; MAX_TASK];

pub fn task_create(task: extern "C" fn()) {
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13 changes: 13 additions & 0 deletions xtensa-lx-rt/src/exception/context.rs
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,19 @@ pub struct Context {
pub F15: u32,
}

impl Default for Context {
fn default() -> Self {
Self::new()
}
}

impl Context {
/// Creates a new, zeroed out context.
pub const fn new() -> Self {
unsafe { core::mem::zeroed() }
}
}

extern "Rust" {
/// The exception assembly jumps here once registers have been spilled
fn __exception(cause: ExceptionCause, save_frame: &mut Context);
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