I2C Async - new_with_timeout_async vs using embassy with_timeout

[yanshay]

I'm using I2C async with embassy.
To perform an operation and provide a timeout to that operation I see two options:

• Using new_with_timeout_async (which is a timeout on the device)
• Using embassy with_timeout on the operation (providing a duration to limit operation waiting time)

My questions:

1. What is the timeout measuring in the case new_with_timeout_async? Is it on the entire operation or on just every I2C ack or something else?
2. s there technically at I2C level a difference when using the new_with_timeout_async (like maybe it stops the operation on the bus when timeout occurs) vs. using embassy to timeout (maybe in that case the operation continues the can't start a new operation later because the I2C is sort of 'stuck' with the previous operation because it wasn't issued with timeout and is not aware embassy moved on)?

[liebman]

1. Single bit timeout - used to configure the timeout for receiving a data bit in APB clock cycles
2. Embassy timeout would drop the future and that should cancel the operation.

[yanshay]

Thanks.

1. What does it mean in I2C to have a timeout on data bit? I2C relies on a clock so whatever the device puts there is fine. The only thing that's expected is the Ack, so is it timeout for the Ack maybe?

This is what I see in logic analyzer, the timeout is measured between which two points?

[liebman]

This timeout is for SCL being held low by the slave (like when clock stretching). Looking at the TRM for the esp32s3 and esp32c3 the timeouts are described:

The I2C controller has three types of timeout control, namely timeout control for SCL_FSM, for SCL_MAIN_FSM, and for the SCL line. The first two are always enabled, while the third is configurable.

When SCL_FSM remains unchanged for more than 2^I2C_SCL_ST _T O_I2C clock cycles, an I2C_SCL_ST_TO_INT interrupt is triggered, and then SCL_FSM goes to idle state. The value of I2C_SCL_ST_TO_I2C should be less than or equal to 22, which means SCL_FSM could remain unchanged for 2^22 I2C_SCLK clock cycles at most before the interrupt is generated.

When SCL_MAIN_FSM remains unchanged for more than 2^2C_SCL_MAIN_ST_TO_I2C clock cycles, an I2C_SCL_MAIN_ST_TO_INT interrupt is triggered, and then SCL_MAIN_FSM goes to idle state. The value of I2C_SCL_MAIN_ST_TO_I2C should be less than or equal to 22, which means SCL_MAIN_FSM could remain unchanged for 2^22 I2C_SCLK clock cycles at most before the interrupt is generated.

Timeout control for SCL is enabled by setting I2C_TIME_OUT_EN. When the level of SCL remains unchanged for more than I2C_TIME_OUT_VALUE clock cycles, an I2C_TIME_OUT_INT interrupt is triggered, and then the I2C bus goes to idle state.

That last one is the one being set in new_with_timeout_async()