Fix clippy warnings, update READMEs

README.md

@@ -62,11 +62,13 @@ There are a number of other crates within the [esp-rs organization] which can be
 | :-------------: | :----------------------------------------------------------------------------: |
 |   [esp-alloc]   |                        A simple `no_std` heap allocator                        |
 | [esp-backtrace] |                 Backtrace support for bare-metal applications                  |
+|  [esp-println]  |                Provides `print!` and `println!` implementations                |
 |  [esp-storage]  | Implementation of [embedded-storage] traits to access unencrypted flash memory |
 
 [esp-rs organization]: https://github.com/esp-rs
 [esp-alloc]: https://github.com/esp-rs/esp-alloc
 [esp-backtrace]: https://github.com/esp-rs/esp-backtrace
+[esp-println]: https://github.com/esp-rs/esp-println
 [esp-storage]: https://github.com/esp-rs/esp-storage
 [embedded-storage]: https://github.com/rust-embedded-community/embedded-storage
 

esp-hal-common/Cargo.toml

@@ -57,11 +57,11 @@ esp32s2 = { version = "0.6.0",  features = ["critical-section"], optional = true
 esp32s3 = { version = "0.9.0",  features = ["critical-section"], optional = true }
 
 [features]
-esp32   = ["esp32/rt"  , "procmacros/xtensa", "xtensa-lx-rt/esp32",   "xtensa-lx/esp32",   "critical-section/restore-state-u32", "lock_api"]
-esp32c2 = ["esp32c2/rt", "procmacros/riscv" , "riscv", "riscv-atomic-emulation-trap",      "critical-section/restore-state-u8"]
-esp32c3 = ["esp32c3/rt", "procmacros/riscv" , "riscv", "riscv-atomic-emulation-trap",      "critical-section/restore-state-u8"]
-esp32s2 = ["esp32s2/rt", "procmacros/xtensa", "xtensa-lx-rt/esp32s2", "xtensa-lx/esp32s2", "critical-section/restore-state-u32", "esp-synopsys-usb-otg", "usb-device"]
-esp32s3 = ["esp32s3/rt", "procmacros/xtensa", "xtensa-lx-rt/esp32s3", "xtensa-lx/esp32s3", "critical-section/restore-state-u32", "lock_api", "esp-synopsys-usb-otg", "usb-device"]
+esp32   = ["esp32/rt"  , "xtensa", "xtensa-lx/esp32",   "xtensa-lx-rt/esp32",   "lock_api"]
+esp32c2 = ["esp32c2/rt", "riscv"]
+esp32c3 = ["esp32c3/rt", "riscv"]
+esp32s2 = ["esp32s2/rt", "xtensa", "xtensa-lx/esp32s2", "xtensa-lx-rt/esp32s2",             "esp-synopsys-usb-otg", "usb-device"]
+esp32s3 = ["esp32s3/rt", "xtensa", "xtensa-lx/esp32s3", "xtensa-lx-rt/esp32s3", "lock_api", "esp-synopsys-usb-otg", "usb-device"]
 
 # Implement the `embedded-hal==1.0.0-alpha.x` traits
 eh1 = ["embedded-hal-1", "embedded-hal-nb"]
@@ -76,8 +76,12 @@ ufmt = ["ufmt-write"]
 vectored = ["procmacros/interrupt"]
 
 # Implement the `embedded-hal-async==1.0.0-alpha.x` traits
-async = ["embedded-hal-async", "eh1", "embassy-sync"]
+async   = ["embedded-hal-async", "eh1", "embassy-sync"]
 embassy = ["embassy-time"]
 
 embassy-time-systick = []
-embassy-time-timg = []
+embassy-time-timg    = []
+
+# Architecture-specific features (intended for internal use)
+riscv  = ["dep:riscv", "critical-section/restore-state-u8",  "procmacros/riscv", "riscv-atomic-emulation-trap"]
+xtensa = [             "critical-section/restore-state-u32", "procmacros/xtensa"]

esp-hal-common/README.md

@@ -10,6 +10,7 @@
 This crate should not be used directly; you should use one of the device-specific HAL crates instead:
 
 - [esp32-hal](../esp32-hal/README.md)
+- [esp32c2-hal](../esp32c2-hal/README.md)
 - [esp32c3-hal](../esp32c3-hal/README.md)
 - [esp32s2-hal](../esp32s2-hal/README.md)
 - [esp32s3-hal](../esp32s3-hal/README.md)

esp-hal-common/src/sha.rs

@@ -17,12 +17,12 @@ use crate::pac::SHA;
 
 const ALIGN_SIZE: usize = core::mem::size_of::<u32>();
 
-// ESP32 does reversed order 
+// ESP32 does reversed order
 #[cfg(esp32)]
 const U32_FROM_BYTES: fn([u8; 4]) -> u32 = u32::from_be_bytes;
 
 #[cfg(not(esp32))]
-const U32_FROM_BYTES: fn([u8; 4]) -> u32 = u32::from_ne_bytes; 
+const U32_FROM_BYTES: fn([u8; 4]) -> u32 = u32::from_ne_bytes;
 
 // The alignment helper helps you write to registers that only accepts u32 using
 // regular u8s (bytes) It keeps a write buffer of 4 u8 (could in theory be 3 but
@@ -292,6 +292,7 @@ impl Sha {
             ShaMode::SHA1 | ShaMode::SHA256 => 64,
             #[cfg(not(esp32))]
             ShaMode::SHA224 => 64,
+            #[cfg(not(any(esp32c2, esp32c3)))]
             _ => 128,
         };
     }
@@ -493,20 +494,18 @@ impl Sha {
         }
 
         unsafe {
-
             let digest_ptr = self.output_ptr();
             let out_ptr = output.as_mut_ptr() as *mut u32;
             let digest_out = core::cmp::min(self.digest_length(), output.len()) / ALIGN_SIZE;
             for i in 0..digest_out {
                 #[cfg(not(esp32))]
                 out_ptr.add(i).write(*digest_ptr.add(i));
-                // ESP32 does reversed order 
+                // ESP32 does reversed order
                 #[cfg(esp32)]
                 out_ptr.add(i).write((*digest_ptr.add(i)).to_be());
-            } 
+            }
         }
 
-
         Ok(())
     }
 

esp32c3-hal/build.rs

@@ -153,21 +153,18 @@ fn check_opt_level() {
         return;
     }
 
-    match env::var_os("OPT_LEVEL") {
-        Some(ref opt_level) => {
-            if opt_level == "z" {
-                println!(
-                    "{}",
-                    OPT_LEVEL_Z_MSG
-                        .lines()
-                        .into_iter()
-                        .map(|l| format!("cargo:warning={l}"))
-                        .collect::<Vec<String>>()
-                        .join("\n")
-                );
-                exit(1);
-            }
+    if let Some(ref opt_level) = env::var_os("OPT_LEVEL") {
+        if opt_level == "z" {
+            println!(
+                "{}",
+                OPT_LEVEL_Z_MSG
+                    .lines()
+                    .into_iter()
+                    .map(|l| format!("cargo:warning={l}"))
+                    .collect::<Vec<String>>()
+                    .join("\n")
+            );
+            exit(1);
         }
-        _ => {}
     }
 }