Add CI for ESP #96
Add CI for ESP #96
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Rebased since #97 |
.github/workflows/ci.yml
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| - name: Build | RISCV-ULP-HAL feature | ||
| run: cargo build --features riscv-ulp-hal --no-default-features --target riscv32imc-unknown-none-elf -Zbuild-std=core,panic_abort -Zbuild-std-features=panic_immediate_abort | ||
| run: cargo build --features riscv-ulp-hal --no-default-features --target ${{ matrix.target }} -Zbuild-std=core,panic_abort -Zbuild-std-features=panic_immediate_abort |
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I am a bit confused. What target is this supposed to have? xtensa-esp32s2-espidf, riscv32imc-esp-espidf, ${{ matrix.target }} or something else?
Also judging from lib.rs:
#[cfg(all(feature = "riscv-ulp-hal", not(esp32s2)))]
compile_error!("Feature `ulp` is currently only supported on esp32s2");
we are supposed to be targeting the esp32s2 device, but compiling for its riscv-coprocessor? What flags should we use to tell cargo this?
Also, perhaps semi unrelated, looking at IDF-doc both S2 and S3 have this thing? Would it be as trivial as simply enable it for the S3 aswell?
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I think we can just remove this part I think. The RISC-V ulp hal has to be compiled with riscv32imc-unknown-none-elf so no point adding this test to the xtensa target matrix.
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Rebased and cleaned up |
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Perfect, thanks @usbalbin! |
From what I understand CI is currently only run for the ESP32-C3. This PR adds a github workflow for the ESP32. I believe this could be useful since some code is not active when building for the ESP32-C3.
Suggestions are welcome. Here is the result of the run.