Merge pull request #47 from esp-rs/bugfix/allow-interrupt-level-preem…

…ption allow interrupt level preemption
esp-rs · Jul 20, 2022 · 654c930 · 654c930
2 parents 70c56b1 + 439aeda
commit 654c930
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Showing 2 changed files with 6 additions and 2 deletions.
diff --git a/Cargo.toml b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "xtensa-lx-rt"
-version = "0.12.0"
+version = "0.13.0"
 description = "Low level access for Xtensa LX processors"
 categories = ["embedded", "hardware-support", "no-std"]
 keywords = ["xtensa", "lx", "register", "peripheral"]

diff --git a/src/exception/assembly_esp32.rs b/src/exception/assembly_esp32.rs
@@ -493,6 +493,10 @@ unsafe extern "C" fn __default_naked_exception() {
         j       .RestoreContext
 
         .Level1Interrupt:
+        movi    a0, (1 | PS_WOE)          // set PS.INTLEVEL accordingly
+        wsr     a0, PS
+        rsync
+
         movi    a6, 1                     // put interrupt level in a6 = a2 in callee
         mov     a7, sp                    // put address of save frame in a7=a3 in callee
         call4   __level_1_interrupt       // call handler <= actual call!
@@ -569,7 +573,7 @@ global_asm!(
     .macro HANDLE_INTERRUPT_LEVEL level
     SAVE_CONTEXT \level
 
-    movi    a0, (PS_INTLEVEL_EXCM | PS_WOE)
+    movi    a0, (\level | PS_WOE)
     wsr     a0, PS
     rsync