esp8266 · earlephilhower · Mar 15, 2021 · Jan 3, 2020 · Dec 22, 2020 · Dec 22, 2020
diff --git a/boards.txt b/boards.txt
diff --git a/cores/esp8266/Esp.cpp b/cores/esp8266/Esp.cpp
@@ -29,7 +29,6 @@
 
 #include "coredecls.h"
 #include "umm_malloc/umm_malloc.h"
-// #include "core_esp8266_vm.h"
 #include <pgmspace.h>
 
 extern "C" {
@@ -972,22 +971,11 @@ String EspClass::getSketchMD5()
     return result;
 }
 
-void EspClass::enableVM()
-{
-#ifdef UMM_HEAP_EXTERNAL
-    if (!vmEnabled)
-        install_vm_exception_handler();
-    vmEnabled = true;
-#endif
-}
-
 void EspClass::setExternalHeap()
 {
 #ifdef UMM_HEAP_EXTERNAL
-    if (vmEnabled) {
-        if (!umm_push_heap(UMM_HEAP_EXTERNAL)) {
-            panic();
-        }
+    if (!umm_push_heap(UMM_HEAP_EXTERNAL)) {
+        panic();
     }
 #endif
 }
@@ -1004,10 +992,8 @@ void EspClass::setIramHeap()
 void EspClass::setDramHeap()
 {
 #if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM)
-    if (vmEnabled) {
-        if (!umm_push_heap(UMM_HEAP_DRAM)) {
-            panic();
-        }
+    if (!umm_push_heap(UMM_HEAP_DRAM)) {
+        panic();
     }
 #elif defined(UMM_HEAP_IRAM)
     if (!umm_push_heap(UMM_HEAP_DRAM)) {
@@ -1019,10 +1005,8 @@ void EspClass::setDramHeap()
 void EspClass::resetHeap()
 {
 #if defined(UMM_HEAP_EXTERNAL) && !defined(UMM_HEAP_IRAM)
-    if (vmEnabled) {
-        if (!umm_pop_heap()) {
-            panic();
-        }
+    if (!umm_pop_heap()) {
+        panic();
     }
 #elif defined(UMM_HEAP_IRAM)
     if (!umm_pop_heap()) {

diff --git a/cores/esp8266/Esp.h b/cores/esp8266/Esp.h
@@ -215,13 +215,6 @@ class EspClass {
 #else
         uint32_t getCycleCount();
 #endif // !defined(CORE_MOCK)
-        /**
-         * @brief Installs VM exception handler to support External memory (Experimental)
-         *
-         * @param none
-         * @return none
-         */
-        void enableVM();
         /**
          * @brief Push current Heap selection and set Heap selection to DRAM.
          *
@@ -252,9 +245,6 @@ class EspClass {
          */
         void resetHeap();
     private:
-#ifdef UMM_HEAP_EXTERNAL
-        bool vmEnabled = false;
-#endif
         /**
          * @brief Replaces @a byteCount bytes of a 4 byte block on flash
          *

diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp
@@ -37,6 +37,7 @@ extern "C" {
 #include "flash_quirks.h"
 #include <umm_malloc/umm_malloc.h>
 #include <core_esp8266_non32xfer.h>
+#include "core_esp8266_vm.h"
 
 
 #define LOOP_TASK_PRIORITY 1
@@ -348,9 +349,14 @@ extern "C" void user_init(void) {
 
     cont_init(g_pcont);
 
+#if defined(UMM_HEAP_EXTERNAL)
+    install_vm_exception_handler();
+#endif
+
 #if defined(NON32XFER_HANDLER) || defined(MMU_IRAM_HEAP)
     install_non32xfer_exception_handler();
 #endif
+
 #if defined(MMU_IRAM_HEAP)
     umm_init_iram();
 #endif

diff --git a/cores/esp8266/core_esp8266_non32xfer.cpp b/cores/esp8266/core_esp8266_non32xfer.cpp
@@ -64,51 +64,10 @@ static
 IRAM_ATTR void non32xfer_exception_handler(struct __exception_frame *ef, int cause)
 {
   do {
-    /*
-       In adapting the public domain version, a crash would come or go away with
-       the slightest unrelated changes elsewhere in the function. Observed that
-       register a15 was used for epc1, then clobbered by `rsr.` I now believe a
-       "&" on the output register would have resolved the problem.
-
-       However, I have refactored the Extended ASM to reduce and consolidate
-       register usage and corrected the issue.
-
-       The positioning of the Extended ASM block (as early as possible in the
-       compiled function) is in part controlled by the immediate need for
-       output variable `insn`. This placement aids in getting excvaddr read as
-       early as possible.
-     */
     uint32_t insn, excvaddr;
-#if 1
-    {
-      uint32_t tmp;
-      __asm__ (
-        "rsr.excvaddr %[vaddr]\n\t"             /* Read faulting address as early as possible */
-        "movi.n %[tmp],  ~3\n\t"                /* prepare a mask for the EPC */
-        "and    %[tmp],  %[tmp],  %[epc]\n\t"   /* apply mask for 32-bit aligned base */
-        "ssa8l  %[epc]\n\t"                     /* set up shift register for src op */
-        "l32i   %[insn], %[tmp],  0\n\t"        /* load part 1 */
-        "l32i   %[tmp],  %[tmp],  4\n\t"        /* load part 2 */
-        "src    %[insn], %[tmp],  %[insn]\n\t"  /* right shift to get faulting instruction */
-        : [vaddr]"=&r"(excvaddr), [insn]"=&r"(insn), [tmp]"=&r"(tmp)
-        : [epc]"r"(ef->epc) :);
-    }
 
-#else
-    {
-      __asm__ __volatile__ ("rsr.excvaddr %0;" : "=r"(excvaddr):: "memory");
-      /*
-        "C" reference code for the ASM to document intent.
-        May also prove useful when issolating possible issues with Extended ASM,
-        optimizations, new compilers, etc.
-      */
-      uint32_t epc = ef->epc;
-      uint32_t *pWord = (uint32_t *)(epc & ~3);
-      uint64_t big_word = ((uint64_t)pWord[1] << 32) | pWord[0];
-      uint32_t pos = (epc & 3) * 8;
-      insn = (uint32_t)(big_word >>= pos);
-    }
-#endif
+    /* Extract instruction and faulting data address */
+    __EXCEPTION_HANDLER_PREAMBLE(ef, excvaddr, insn);
 
     uint32_t what = insn & LOAD_MASK;
     uint32_t valmask = 0;

diff --git a/cores/esp8266/core_esp8266_non32xfer.h b/cores/esp8266/core_esp8266_non32xfer.h
@@ -7,6 +7,54 @@ extern "C" {
 
 extern void install_non32xfer_exception_handler();
 
+
+    /*
+       In adapting the public domain version, a crash would come or go away with
+       the slightest unrelated changes elsewhere in the function. Observed that
+       register a15 was used for epc1, then clobbered by `rsr.` I now believe a
+       "&" on the output register would have resolved the problem.
+
+       However, I have refactored the Extended ASM to reduce and consolidate
+       register usage and corrected the issue.
+
+       The positioning of the Extended ASM block (as early as possible in the
+       compiled function) is in part controlled by the immediate need for
+       output variable `insn`. This placement aids in getting excvaddr read as
+       early as possible.
+     */
+
+#if 0
+    {
+      __asm__ __volatile__ ("rsr.excvaddr %0;" : "=r"(excvaddr):: "memory");
+      /*
+        "C" reference code for the ASM to document intent.
+        May also prove useful when issolating possible issues with Extended ASM,
+        optimizations, new compilers, etc.
+      */
+      uint32_t epc = ef->epc;
+      uint32_t *pWord = (uint32_t *)(epc & ~3);
+      uint64_t big_word = ((uint64_t)pWord[1] << 32) | pWord[0];
+      uint32_t pos = (epc & 3) * 8;
+      insn = (uint32_t)(big_word >>= pos);
+    }
+#endif
+
+#define __EXCEPTION_HANDLER_PREAMBLE(ef, excvaddr, insn) \
+    { \
+      uint32_t tmp; \
+      __asm__ ( \
+        "rsr.excvaddr %[vaddr]\n\t"             /* Read faulting address as early as possible */ \
+        "movi.n %[tmp],  ~3\n\t"                /* prepare a mask for the EPC */ \
+        "and    %[tmp],  %[tmp],  %[epc]\n\t"   /* apply mask for 32-bit aligned base */ \
+        "ssa8l  %[epc]\n\t"                     /* set up shift register for src op */ \
+        "l32i   %[insn], %[tmp],  0\n\t"        /* load part 1 */ \
+        "l32i   %[tmp],  %[tmp],  4\n\t"        /* load part 2 */ \
+        "src    %[insn], %[tmp],  %[insn]\n\t"  /* right shift to get faulting instruction */ \
+        : [vaddr]"=&r"(excvaddr), [insn]"=&r"(insn), [tmp]"=&r"(tmp) \
+        : [epc]"r"(ef->epc) :); \
+    }
+
+
 #ifdef __cplusplus
 }
 #endif