Merge branch 'feature/gdma_support_h2' into 'master'

gdma: support esp32h2

Closes IDF-6222 and IDF-6238

See merge request espressif/esp-idf!21932

components/bootloader_support/src/bootloader_mem.c

@@ -12,15 +12,15 @@
 #include "bootloader_mem.h"
 #include "esp_cpu.h"
 
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
 #include "soc/hp_apm_reg.h"
 #include "soc/lp_apm_reg.h"
 #include "soc/lp_apm0_reg.h"
 #endif
 
 void bootloader_init_mem(void)
 {
-#if CONFIG_IDF_TARGET_ESP32C6
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
     // disable apm filter // TODO: IDF-5909
     REG_WRITE(LP_APM_FUNC_CTRL_REG, 0);
     REG_WRITE(LP_APM0_FUNC_CTRL_REG, 0);

components/esp_hw_support/CMakeLists.txt

@@ -47,7 +47,7 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "dma/async_memcpy_impl_cp_dma.c")
     endif()
 
-    if(CONFIG_SOC_GDMA_SUPPORTED OR CONFIG_SOC_CP_DMA_SUPPORTED)
+    if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED)
         list(APPEND srcs "dma/esp_async_memcpy.c")
     endif()
 

components/esp_hw_support/dma/async_memcpy_impl_gdma.c

@@ -15,6 +15,9 @@
 #include "esp_attr.h"
 #include "esp_err.h"
 #include "esp_async_memcpy_impl.h"
+#if SOC_APM_SUPPORTED
+#include "hal/apm_ll.h"
+#endif
 
 IRAM_ATTR static bool async_memcpy_impl_rx_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {
@@ -71,6 +74,14 @@ esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl)
     gdma_apply_strategy(impl->tx_channel, &strategy_config);
     gdma_apply_strategy(impl->rx_channel, &strategy_config);
 
+#if SOC_APM_SUPPORTED
+    // APM GDMA master for M2M should have the same offset of its GDMA trigger
+    ESP_STATIC_ASSERT((APM_LL_MASTER_GDMA_M2M - 16) == SOC_GDMA_TRIG_PERIPH_M2M0);
+    // APM strategy: trusted mode
+    // TODO: IDF-5354 GDMA for M2M usage only need read and write permissions, we should disable the execute permission by the APM controller
+    apm_ll_set_master_secure_mode(APM_LL_MASTER_GDMA_M2M, APM_LL_SECURE_MODE_TEE);
+#endif // SOC_APM_SUPPORTED
+
     gdma_rx_event_callbacks_t cbs = {
         .on_recv_eof = async_memcpy_impl_rx_eof_callback
     };

components/esp_hw_support/include/esp_private/gdma.h

@@ -32,7 +32,7 @@ typedef struct gdma_channel_t *gdma_channel_handle_t;
  */
 typedef enum {
     GDMA_TRIG_PERIPH_M2M,  /*!< GDMA trigger peripheral: M2M */
-    GDMA_TRIG_PERIPH_UART, /*!< GDMA trigger peripheral: UART */
+    GDMA_TRIG_PERIPH_UHCI, /*!< GDMA trigger peripheral: UHCI */
     GDMA_TRIG_PERIPH_SPI,  /*!< GDMA trigger peripheral: SPI */
     GDMA_TRIG_PERIPH_I2S,  /*!< GDMA trigger peripheral: I2S */
     GDMA_TRIG_PERIPH_AES,  /*!< GDMA trigger peripheral: AES */
@@ -126,13 +126,13 @@ typedef struct {
  */
 typedef struct {
     gdma_trigger_peripheral_t periph; /*!< Target peripheral which will trigger DMA operations */
-    int instance_id;                  /*!< Peripheral instance ID. Supported IDs are listed in `soc/gdma_channel.h`, e.g. SOC_GDMA_TRIG_PERIPH_UART0 */
+    int instance_id;                  /*!< Peripheral instance ID. Supported IDs are listed in `soc/gdma_channel.h`, e.g. SOC_GDMA_TRIG_PERIPH_UHCI0 */
 } gdma_trigger_t;
 
 /**
  * @brief Helper macro to initialize GDMA trigger
  * @note value of `peri` must be selected from `gdma_trigger_peripheral_t` enum.
- *       e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_UART,0)
+ *       e.g. GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S,0)
  *
  */
 #define GDMA_MAKE_TRIGGER(peri, id) \

components/hal/esp32c6/include/hal/apm_ll.h

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/tee_reg.h"
+
+#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief APM Master ID
+ */
+typedef enum {
+    APM_LL_MASTER_HPCORE       = 0,
+    APM_LL_MASTER_LPCORE       = 1,
+    APM_LL_MASTER_REGDMA       = 2,
+    APM_LL_MASTER_SDIOSLV      = 3,
+    APM_LL_MASTER_MODEM        = 4,
+    APM_LL_MASTER_MEM_MONITOR  = 5,
+    APM_LL_MASTER_TRACE        = 6,
+    APM_LL_MASTER_GDMA_SPI2    = 16,
+    APM_LL_MASTER_GDMA_M2M     = 17, // a dummy GDMA trigger, used by M2M copy
+    APM_LL_MASTER_GDMA_UHCI0   = 18,
+    APM_LL_MASTER_GDMA_I2S0    = 19,
+    APM_LL_MASTER_GDMA_AES     = 22,
+    APM_LL_MASTER_GDMA_SHA     = 23,
+    APM_LL_MASTER_GDMA_ADC     = 24,
+    APM_LL_MASTER_GDMA_PARLIO  = 25,
+} apm_ll_master_id_t;
+
+/**
+ * @brief APM Secure Mode
+ */
+typedef enum {
+    APM_LL_SECURE_MODE_TEE = 0,  /* Trusted execution environment mode */
+    APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */
+    APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */
+    APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */
+} apm_ll_secure_mode_t;
+
+/**
+ * @brief Set secure mode
+ *
+ * @param master_id APM master ID
+ * @param mode Secure mode
+ */
+static inline void apm_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t mode)
+{
+    REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), mode);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32c6/include/hal/gdma_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "soc/gdma_struct.h"
 #include "soc/gdma_reg.h"
 #include "soc/soc_etm_source.h"
+#include "soc/gdma_channel.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -89,8 +90,8 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo
     dev->channel[channel].in.in_conf0.mem_trans_en = enable;
     if (enable) {
         // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a dummy value
-        dev->channel[channel].in.in_peri_sel.peri_in_sel = 1;
-        dev->channel[channel].out.out_peri_sel.peri_out_sel = 1;
+        dev->channel[channel].in.in_peri_sel.peri_in_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
+        dev->channel[channel].out.out_peri_sel.peri_out_sel = SOC_GDMA_TRIG_PERIPH_M2M0;
     }
 }
 

components/hal/esp32h2/include/hal/apm_ll.h

@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/tee_reg.h"
+
+#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief APM Master ID
+ */
+typedef enum {
+    APM_LL_MASTER_HPCORE       = 0,
+    APM_LL_MASTER_LPCORE       = 1,
+    APM_LL_MASTER_REGDMA       = 2,
+    APM_LL_MASTER_SDIOSLV      = 3,
+    APM_LL_MASTER_MODEM        = 4,
+    APM_LL_MASTER_MEM_MONITOR  = 5,
+    APM_LL_MASTER_TRACE        = 6,
+    APM_LL_MASTER_GDMA_SPI2    = 16,
+    APM_LL_MASTER_GDMA_M2M     = 17, // a dummy GDMA trigger, used by M2M copy
+    APM_LL_MASTER_GDMA_UHCI0   = 18,
+    APM_LL_MASTER_GDMA_I2S0    = 19,
+    APM_LL_MASTER_GDMA_AES     = 22,
+    APM_LL_MASTER_GDMA_SHA     = 23,
+    APM_LL_MASTER_GDMA_ADC     = 24,
+    APM_LL_MASTER_GDMA_PARLIO  = 25,
+} apm_ll_master_id_t;
+
+/**
+ * @brief APM Secure Mode
+ */
+typedef enum {
+    APM_LL_SECURE_MODE_TEE = 0,  /* Trusted execution environment mode */
+    APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 (need to configure APM strategy for this mode) */
+    APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 (need to configure APM strategy for this mode) */
+    APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 (need to configure APM strategy for this mode) */
+} apm_ll_secure_mode_t;
+
+/**
+ * @brief Set secure mode
+ *
+ * @param master_id APM master ID
+ * @param mode Secure mode
+ */
+static inline void apm_ll_set_master_secure_mode(apm_ll_master_id_t master_id, apm_ll_secure_mode_t mode)
+{
+    REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), mode);
+}
+
+#ifdef __cplusplus
+}
+#endif