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Releases: freand76/digsim

Release v0.6.0

10 Oct 11:51
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  • Block bad pyside version 6.8.0

Release v0.5.0

05 Oct 08:26
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  • Added pytest verilog testbench example
  • Update python dependencies (yosys/pydantic/pyside6/...)
  • Update to ruff 0.6.9 (And fix code that ruff thought was bad)
  • Drop python 3.8 support

Release v0.4.0

10 Apr 15:54
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  • Make it possible to use locally installed yosys
  • Use ruff for python formatting and linting of code
  • Fix issue #3 (AttributeError when trying to delete objects)

Release v0.3.1

16 Dec 17:56
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  • Fix path in examples to work with github action

Release v0.3.0

16 Dec 17:15
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  • Use relative path in examples (for windows / yosys)
  • Use alternative pexpect spawn function in windows

Release v0.2.0

16 Dec 14:23
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  • Use yowasp-yoysys for synthesis

Release v0.1.0

09 Dec 12:45
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  • Fix bug when detecting number of modules with yosys 0.9
  • Improve error handling for yosys component
  • Remove settings from pushbutton and switch

v0.0.1 - First Release

07 Dec 16:50
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  • Simulation of a digital circuit using a python
  • Simulation of a yosys netlist using a python
  • GUI application to build and simulate circuit