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add initial instruction expansion for tile configuration -- no handli…
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…ng yet, only copying
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Michael Allen Goldstein committed Feb 29, 2024
1 parent 5370baf commit f8e2fd2
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Showing 4 changed files with 146 additions and 24 deletions.
25 changes: 25 additions & 0 deletions src/trace_read.h
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Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,30 @@ POSSIBILITY OF SUCH DAMAGE.
/// read/write required size only.
///////////////////////////////////////////////////////////////////////////////////////////////

typedef struct Tile_info {
uint8_t palette; // selects the supported configuration of the tiles that will be used
uint8_t start_row; // used for storing the restart values for interrupted operations
uint8_t buf0[14]; // reserved, must be 0
uint16_t tile0_colsb; // Tile 0 bytes per row
uint16_t tile1_colsb; // Tile 1 bytes per row
uint16_t tile2_colsb; // Tile 2 bytes per row
uint16_t tile3_colsb; // Tile 3 bytes per row
uint16_t tile4_colsb; // Tile 4 bytes per row
uint16_t tile5_colsb; // Tile 5 bytes per row
uint16_t tile6_colsb; // Tile 6 bytes per row
uint16_t tile7_colsb; // Tile 7 bytes per row
uint8_t buf1[14]; // reserved, must be 0
uint8_t tile0_rows; // Tile 0 rows
uint8_t tile1_rows; // Tile 1 rows
uint8_t tile2_rows; // Tile 2 rows
uint8_t tile3_rows; // Tile 3 rows
uint8_t tile4_rows; // Tile 4 rows
uint8_t tile5_rows; // Tile 5 rows
uint8_t tile6_rows; // Tile 6 rows
uint8_t tile7_rows; // Tile 7 rows
uint8_t buf2[8]; // reserved, must be 0
} tile_info_t;

typedef struct trace_info_s {
trace_info_s();
virtual ~trace_info_s();
Expand All @@ -87,6 +111,7 @@ typedef struct trace_info_cpu_s {
bool m_write_flg; /**< write flag */
uint8_t m_num_ld; /**< number of load operations */
uint8_t m_size; /**< instruction size */
tile_info_t m_tile_info; /** info regarding tile configuration */
// dynamic information
uint64_t m_ld_vaddr1; /**< load address 1 */
uint64_t m_ld_vaddr2; /**< load address 2 */
Expand Down
39 changes: 22 additions & 17 deletions src/trace_read_cpu.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -901,27 +901,32 @@ inst_info_s *cpu_decoder_c::convert_pinuop_to_t_uop(void *trace_info,
if (pi->m_opcode == XED_CATEGORY_AMX_TILE) {
// handle AMX tile instructions
bool is_amx_mem = (pi->m_has_st) || (pi->m_num_ld > 0);
bool is_amx_config = false; // TODO: add way to read this and confirm it
dyn_uop_counter = 1;

if (is_amx_mem) {
int rep_counter = 1;
int rep_dir = 0;
int tileload_type = -1;

if (pi->m_has_st) {
trace_uop[0]->m_mem_type = MEM_ST;
if (is_amx_config) {
// load config data regarding tiles
} else {
trace_uop[0]->m_mem_type = MEM_LD;
trace_uop[0]->m_mem_size = pi->m_mem_read_size;
DEBUG_CORE(
core_id,
"AMX_TILE_MEM core_id:%d thread_id:%d pc:0x%llx opcode:%d"
"mem_read_size:%d dyn_uop_counter:%d \n",
core_id, sim_thread_id, (Addr)(pi->m_instruction_addr),
static_cast<int>(pi->m_opcode), pi->m_mem_read_size,
dyn_uop_counter
);
ASSERTM(pi->m_num_ld > 0 && "invalid number of loads");
int rep_counter = 1;
int rep_dir = 0;
int tileload_type = -1;

if (pi->m_has_st) {
trace_uop[0]->m_mem_type = MEM_ST;
} else {
trace_uop[0]->m_mem_type = MEM_LD;
trace_uop[0]->m_mem_size = pi->m_mem_read_size;
DEBUG_CORE(
core_id,
"AMX_TILE_MEM core_id:%d thread_id:%d pc:0x%llx opcode:%d"
"mem_read_size:%d dyn_uop_counter:%d \n",
core_id, sim_thread_id, (Addr)(pi->m_instruction_addr),
static_cast<int>(pi->m_opcode), pi->m_mem_read_size,
dyn_uop_counter
);
ASSERT(pi->m_num_ld > 0 && "invalid number of loads");
}
}
} // is_amx_mem

Expand Down
78 changes: 72 additions & 6 deletions tools/x86_trace_generator/trace_generator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ using namespace INSTLIB;

#define DUMMY_THREAD 100000

//#define VERBOSE
#define VERBOSE

#define THREAD_ENABLE_CHECK(tid) \
if ((tid) == DUMMY_THREAD) \
Expand Down Expand Up @@ -243,12 +243,73 @@ VOID AMXGEMM(UINT32 dst, UINT32 a, UINT32 b, THREADID tid) {
}
}

VOID AMXConfig(UINT32 dst, THREADID tid) {
/*
layout:
Bytes | field | description
0 palette selects the supported configuration of the tiles that will be used
1 start_row used for storing the restart values for interrupted operations
2-15 reserved, must be 0
16-17 tile0.colsb Tile 0 bytes per row
18-19 tile1.colsb Tile 1 bytes per row
20-21 tile2.colsb Tile 2 bytes per row
22-23 tile3.colsb Tile 3 bytes per row
24-25 tile4.colsb Tile 4 bytes per row
26-27 tile5.colsb Tile 5 bytes per row
28-29 tile6.colsb Tile 6 bytes per row
30-31 tile7.colsb Tile 7 bytes per row
32-47 reserved, must be 0
48 tile0.rows Tile 0 rows
49 tile1.rows Tile 1 rows
50 tile2.rows Tile 2 rows
51 tile3.rows Tile 3 rows
52 tile4.rows Tile 4 rows
53 tile5.rows Tile 5 rows
54 tile6.rows Tile 6 rows
55 tile7.rows Tile 7 rows
56-63 reserved, must be 0
*/
tile_info_t::Tile_info(void) {
this->palette = 0;
this->start_row = 0;
for (int i = 0; i < 14; i++) {
this->buf0[i] = 0;
this->buf1[i] = 0;
if (i < 8) {
this->buf2[i] = 0;
}
}
this->tile0_colsb = 0;
this->tile1_colsb = 0;
this->tile2_colsb = 0;
this->tile3_colsb = 0;
this->tile4_colsb = 0;
this->tile5_colsb = 0;
this->tile6_colsb = 0;
this->tile7_colsb = 0;
this->tile0_rows = 0;
this->tile1_rows = 0;
this->tile2_rows = 0;
this->tile3_rows = 0;
this->tile4_rows = 0;
this->tile5_rows = 0;
this->tile6_rows = 0;
this->tile7_rows = 0;
}

tile_info_t t_info;
VOID AMXConfig(ADDRINT *addr, THREADID tid) {
// TODO: figure out how to get dynamic info from this (rows, row size, etc)
Trace_info *tr_info = trace_info_array[tid];
if (tr_info == nullptr || !PIN_IsAmxActive(tid)) {
return;
}
PIN_SafeCopy(&t_info, addr, 64);

// handle data
tr_info->inst_info.tile_info = t_info;
// load info
tr_info->vaddr1 = *addr;
tr_info->mem_read_size = 64;
}

////////////////////////////////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -645,7 +706,7 @@ void instrument(INS ins)

const ADDRINT iaddr = INS_Address(ins);
Inst_info *info = new Inst_info;
memset(info, 0, sizeof(*info));
memset((void *)info, 0, sizeof(*info));

src_regs.clear();
dst_regs.clear();
Expand Down Expand Up @@ -1051,19 +1112,24 @@ void instrument(INS ins)
);
} else if (INS_Mnemonic(ins) == "LDTILECFG") {
#ifdef VERBOSE
cout << "ldtilecfg" << endl;
//REG base_reg = INS_OperandMemoryBaseReg(ins, 1);
//REG index_reg = INS_OperandMemoryIndexReg(ins, 1);
cout << "ldtilecfg" /*[" << REG_StringShort(base_reg) << "+" << REG_StringShort(index_reg) << "]"*/ << endl;
#endif
// send memory address to copy config data from
info->num_ld = 1;
INS_InsertCall(
ins,
IPOINT_BEFORE, AFUNPTR(AMXConfig),
IARG_UINT32, REG_TMM0, // ???
IARG_MEMORYOP_PTR, 0,
IARG_THREAD_ID,
IARG_END
);
} else if (INS_Mnemonic(ins) == "TILERELEASE") {
#ifdef VERBOSE
cout << "tilerelease" << endl;
#endif
memset((void *)&t_info, 0, sizeof(tile_info_t));
} else {
cerr << "Unsupported AMX instruction: " << INS_Mnemonic(ins) << endl;
exit(-1);
Expand Down Expand Up @@ -1146,7 +1212,7 @@ void ThreadStart(THREADID tid, CONTEXT *ctxt, INT32 flags, void *v)
cerr << "could not allocate memory\n";
return;
}
memset(trace_info, 0, sizeof(Trace_info));
memset((void *)trace_info, 0, sizeof(Trace_info));

stringstream sstream;
sstream << Knob_trace_name.Value() << "_" << threadid << ".raw";
Expand Down
28 changes: 27 additions & 1 deletion tools/x86_trace_generator/trace_generator.h
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,31 @@ struct Thread_info
uint64_t inst_count; /**< Instruction count */
};

typedef struct Tile_info {
Tile_info(void);
UINT8 palette; // selects the supported configuration of the tiles that will be used
UINT8 start_row; // used for storing the restart values for interrupted operations
UINT8 buf0[14]; // reserved, must be 0
UINT16 tile0_colsb; // Tile 0 bytes per row
UINT16 tile1_colsb; // Tile 1 bytes per row
UINT16 tile2_colsb; // Tile 2 bytes per row
UINT16 tile3_colsb; // Tile 3 bytes per row
UINT16 tile4_colsb; // Tile 4 bytes per row
UINT16 tile5_colsb; // Tile 5 bytes per row
UINT16 tile6_colsb; // Tile 6 bytes per row
UINT16 tile7_colsb; // Tile 7 bytes per row
UINT8 buf1[14]; // reserved, must be 0
UINT8 tile0_rows; // Tile 0 rows
UINT8 tile1_rows; // Tile 1 rows
UINT8 tile2_rows; // Tile 2 rows
UINT8 tile3_rows; // Tile 3 rows
UINT8 tile4_rows; // Tile 4 rows
UINT8 tile5_rows; // Tile 5 rows
UINT8 tile6_rows; // Tile 6 rows
UINT8 tile7_rows; // Tile 7 rows
UINT8 buf2[8]; // reserved, must be 0
} tile_info_t;

/**
* Instruction Information
*/
Expand All @@ -82,6 +107,7 @@ struct Inst_info
bool write_flg; // 1bit
uint8_t num_ld; // 2bit
uint8_t size; // 5 bit
tile_info_t tile_info; // 64 bytes
// **** dynamic ****
uint64_t ld_vaddr1; // 4 bytes
uint64_t ld_vaddr2; // 4 bytes
Expand All @@ -91,7 +117,7 @@ struct Inst_info
uint8_t mem_read_size; // 8 bit
uint8_t mem_write_size; // 8 bit
bool rep_dir; // 1 bit
bool actually_taken; // 1 ibt
bool actually_taken; // 1 bit
};

#define BUF_SIZE (10 * sizeof(struct Inst_info))
Expand Down

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