A curated list of awesome RISC-V implementations
| Repository | Language | arch | microarch | Target | License | ⭐ |
|---|---|---|---|---|---|---|
| FWRISC-S | SystemVerilog | rv32i[mc] | FPGA | Apache2 |  |
|
| Ibex | SystemVerilog | rv32imc | 2 stage | ASIC | Apache2 |  |
| Minerva | Python,nMigen | rv32im | 6 stage | FPGA | BSD |  |
| PicoRV32 | Verilog | rv32{i,e}[m][c] | ? | FPGA,ASIC | ISC |  |
| riscv-mini | Scala,Chisel | rv32i | 3 stage | ASIC | BSD |  |
| Rocket | Scala,Chisel | rv32ima | 5? stage | ASIC | BSD |  |
| SERV | Verilog | rv32 | 0-calories | FPGA | ISC |  |
| SweRV | SystemVerilog | rv32imc | 9-stage, dual-issue, superscalar | ASIC | Apache2 |  |
| VexRiscv | Scala,SpinalHDL | rv32i[m][c][a] | 2-5 stage | FPGA | MIT |  |
To the extent possible under law, Aliaksei Chapyzhenka has waived all copyright and related or neighboring rights to this work.