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Multicycle MIPS microarchitecture on Quartus II, focused on Terasic DE0 Development board

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MIPS on Quartus II

Multicycle MIPS microarchitecture on Quartus II 13.0sp1, focused on Terasic DE0 Development board.

The multicycle microarchitecture is based on chapter 7 of Harris' Digital Design and Computer Architecture.

Requirements

All software below can be downloaded for free at https://fpgasoftware.intel.com/13.0sp1/?edition=web

  • Altera Quartus II 13.0sp1 Web Edition
  • ModelSim (bundled with Quartus II 13.0)
  • Cyclone III device support

Instructions

  1. Clone this repository or download as a zip
  2. Make a copy of mips.qsf.default named mips.qsf
  3. Choose a top-level entity (optional): on Quartus II, Project Navigator, Files tab, right-click on the desired file and select "Set as Top-Level Entity"

Simulation/Testbench

Since ModelSim doesn't create project files with relative paths, you will need to create a project and include the files manually. See Kashani-Akhavan's tutorial, sections 4 and 5.

When adding files to ModelSim project, make sure the compile order is correct by adding first the DUT file, and then the testbench file. You can see the files' order on the Project tab.

ModelSim file order

Set the VHDL version to 2008 (View > Properties > VHDL > Use 1076-2008).

When simulating macroblocks (e.g. datapath, control_unit), make sure all its internal blocks are added to the project, otherwise it won't work.

Some testbenches were generated with the aid of Doulos' online tool.

References


2018 — Gutierrez PS

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