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Adding support for synth.tcl to read SystemVerilog files using Surelog. #191

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Sep 18, 2023
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Adding support for synth.tcl to read SystemVerilog files using Surelog. #191

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6 changes: 5 additions & 1 deletion synthesis/synth.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,11 @@ foreach src $srcs {
# Skip empty lines, including the implict one after the last \n delimiter
# for files that end with a newline.
if {$src eq ""} continue
yosys read_verilog -sv -defer $src
if {[info exists ::env(USE_SURELOG_FRONTEND)]} {
yosys read_systemverilog $src
} else {
yosys read_verilog -sv -defer $src
}
}

# read UHDM designs
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