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fix VhdlExtractor.is_array + use setup.cfg + clean #10

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48 changes: 23 additions & 25 deletions doc/conf.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,25 +45,26 @@
master_doc = 'index'

# General information about the project.
project = u'Hdlparse'
copyright = u'2017, Kevin Thibedeau'
author = u'Kevin Thibedeau'
project = 'Hdlparse'
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@michael-etzkorn michael-etzkorn Mar 12, 2022

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The small edits here will conflict with umarcor/doc-btd, but I'm not sure the status of that PR. I'd ideally merge that before doing clean-up here. It seems our intention is to change the name to pyHDLParser since I don't think we can get the PyPI namespace unless we hear back from Kevin.

copyright = '2017, Kevin Thibedeau'
author = 'Kevin Thibedeau'

# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
# built documents.
#


def get_package_version(verfile):
'''Scan the script for the version string'''
version = None
with open(verfile) as fh:
try:
version = [line.split('=')[1].strip().strip("'") for line in fh if \
line.startswith('__version__')][0]
except IndexError:
pass
return version
"""Scan the script for the version string"""
version = None
with open(verfile) as fh:
try:
version = [line.split('=')[1].strip().strip("'") for line in fh if
line.startswith('__version__')][0]
except IndexError:
pass
return version


# The short X.Y version.
version = get_package_version('../hdlparse/minilexer.py')
Expand Down Expand Up @@ -102,13 +103,13 @@ def get_package_version(verfile):
#
# html_theme_options = {}
html_theme_options = {
'description': 'HDL parsing library',
'show_powered_by': False,
'logo_text_align': 'center',
'font_family': 'Verdana, Geneva, sans-serif',
'github_user': 'kevinpt',
'github_repo': 'hdlparse',
'github_button': True
'description': 'HDL parsing library',
'show_powered_by': False,
'logo_text_align': 'center',
'font_family': 'Verdana, Geneva, sans-serif',
'github_user': 'kevinpt',
'github_repo': 'hdlparse',
'github_button': True
}

# Add any paths that contain custom static files (such as style sheets) here,
Expand All @@ -124,12 +125,12 @@ def get_package_version(verfile):
html_sidebars = {
'**': [
'about.html',
'relations.html', # needs 'show_related': True theme option to display
'relations.html', # needs 'show_related': True theme option to display
'localtoc.html',
'projects.html',
'searchbox.html'
],

'index': [
'about.html',
'download.html',
Expand Down Expand Up @@ -196,6 +197,3 @@ def get_package_version(verfile):
author, 'HdlParse', 'One line description of project.',
'Miscellaneous'),
]



2 changes: 2 additions & 0 deletions hdlparse/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
"""Parse Verilog and VHDL files"""
__version__ = '1.1.0'
18 changes: 9 additions & 9 deletions hdlparse/minilexer.py
Original file line number Diff line number Diff line change
@@ -1,20 +1,20 @@
# -*- coding: utf-8 -*-
# Copyright © 2017 Kevin Thibedeau
# Distributed under the terms of the MIT license
"""Minimalistic lexer engine inspired by the PyPigments RegexLexer"""
import re
import logging

"""Minimalistic lexer engine inspired by the PyPigments RegexLexer"""

__version__ = '1.0.7'

log = logging.getLogger(__name__)
handler = logging.StreamHandler()
handler.setFormatter(logging.Formatter('%(name)s - %(levelname)s - %(message)s'))
log.addHandler(handler)

if not log.handlers: # only add the handler if no handlers are already registered
handler = logging.StreamHandler()
handler.setFormatter(logging.Formatter('%(name)s - %(levelname)s - %(message)s'))
log.addHandler(handler)


class MiniLexer(object):
class MiniLexer():
"""Simple lexer state machine with regex matching rules"""

def __init__(self, tokens, flags=re.MULTILINE):
Expand Down Expand Up @@ -53,7 +53,7 @@ def run(self, text):
text (str): Text to apply lexer to

Yields:
A sequence of lexer matches.
A sequence of lexer matches
"""

stack = ['root']
Expand All @@ -66,7 +66,7 @@ def run(self, text):
m = pat.match(text, pos)
if m:
if action:
log.debug(f"Match: {m.group().strip()} -> {action}")
log.debug("Match: %s -> %s", m.group().strip(), action)

yield (pos, m.end() - 1), action, m.groups()

Expand Down
23 changes: 9 additions & 14 deletions hdlparse/verilog_parser.py
Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
# -*- coding: utf-8 -*-
# Copyright © 2017 Kevin Thibedeau
# Distributed under the terms of the MIT license
"""Verilog documentation parser"""
import io
import os
from collections import OrderedDict
from .minilexer import MiniLexer

from hdlparse.minilexer import MiniLexer

"""Verilog documentation parser"""

verilog_tokens = {
# state
Expand All @@ -25,7 +24,7 @@
r'^[\(\s]*(input|inout|output)\s+(reg|supply0|supply1|tri|triand|trior|tri0|tri1|wire|wand|wor)?'
r'\s*(signed)?\s*((\[[^]]+\])+)?',
'module_port_start', 'module_port'),
(r'endmodule', 'end_module', '#pop'),
(r'\bendmodule\b', 'end_module', '#pop'),
(r'/\*', 'block_comment', 'block_comment'),
(r'//#\s*{{(.*)}}\n', 'section_meta'),
(r'//.*\n', None),
Expand Down Expand Up @@ -110,11 +109,12 @@ def parse_verilog_file(fname):
"""Parse a named Verilog file

Args:
fname (str): File to parse.
fname (str): File to parse

Returns:
List of parsed objects.
List of parsed objects
"""
with open(fname, 'rt') as fh:
with open(fname, 'rt', encoding='UTF-8') as fh:
text = fh.read()
return parse_verilog(text)

Expand All @@ -130,25 +130,21 @@ def parse_verilog(text):
lex = VerilogLexer

name = None
kind = None
saved_type = None
mode = 'input'
port_type = 'wire'
param_type = ''

metacomments = []
parameters = []

generics = []
ports = OrderedDict()
sections = []
port_param_index = 0
last_item = None
array_range_start_pos = 0

objects = []

for pos, action, groups in lex.run(text):
for _, action, groups in lex.run(text):
if action == 'metacomment':
comment = groups[0].strip()
if last_item is None:
Expand All @@ -160,7 +156,6 @@ def parse_verilog(text):
sections.append((port_param_index, groups[0]))

elif action == 'module':
kind = 'module'
name = groups[0]
generics = []
ports = OrderedDict()
Expand Down Expand Up @@ -226,7 +221,7 @@ def is_verilog(fname):
Returns:
True when file has a Verilog extension.
"""
return os.path.splitext(fname)[1].lower() in ('.vlog', '.v')
return os.path.splitext(fname)[-1].lower() in ('.vlog', '.v', '.sv')
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The verilog parser currently offers next to no SystemVerilog extension support, so I'm not sure we should add .sv here unless we intend to start adding minimal support. The problem is even if all we did was parse logic, I'm pretty sure something like wire [7:0] logic is valid verilog... We'd ideally want to make it an optional flag.

I am in favor of basic support as I mention here:
#4 (comment)

but we can maybe start a different branch / PR for that?



class VerilogExtractor:
Expand Down
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