Provides a pll4 reset function with all the options to set the
div_select, num, denom values with asserts ensuring bounds are kept
based on the data sheet. It would be nice to assert these at compile
time if possible and could be a future improvement to ensure the pll
options are valid.

The sai clock gating, selection, and divisor settings are also added
enabling the full clocking of a sai peripheral from the audio pll to the
peripheral input clock.

The board clocks for sai1 are setup to generate an appropriate clock for
a 48KHz 16bit stereo i2s stream by default that a wolfson wm8960 codec
can pick up for playback.

SAI can be modeled like a UART in some regards where there are a Tx/Rx
pair. Unlike a UART though SAI in iMXRT can have multiple data channels
connected to the same peripheral. While each channel has its own fifo
and pin they are still part of the same peripheral instance. Meaning the
clock, status, FIFO watermark, and more are all the shared.

This adds some complications. Use of the Tx and Rx together is also
optional, its quite possible only Tx or Rx in use.

So modeling this API requires some interesting use of generics, but in
effect the Sai struct is a builder that enables building a Sai Tx/Rx
optional pair given pins and builder like options.

The goal in the end is to have static const generated register fields
from perhaps a const fn friendly builder type (SaiConfig).

From there a Tx/Rx pair provide functionality for writing
frames of audio samples per channel, managing interrupt masks, checking
status, and enabling/disabling the transmitter or receiver.

In some instances the Tx/Rx pair are *synchronized* meaning between the
pair one will drive the frame sync clock of the other.

This leads to a small potential race at the moment if a Tx and Rx are
setup as synchronized and the tx/rx is enabled/disabled independent of
the other that I can see. I don't have a great way of solving this
particular setup in a safe way at the moment.

Provides a sample application for playing back audio without DMA
directly writing to the FIFO of the SAI peripheral, which should result
in an I2S signaling to the WM8960 codec on the EVK boards. The codec
should then output a nice square wave on one channel and a sine wave on
the other.

The example in this case uses a PIT timer to print the status and a SAI1
interrupt noting a FIFO request to synthesize samples when needed.