Merge pull request #47 from HaoyangLiu/fix-LRU-cache-issue

R4R: Add latest tx to the back of cache list
irisnet · Mar 6, 2019 · add95d4 · add95d4
2 parents 7715be4 + 3079771
commit add95d4
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/mempool/mempool.go b/mempool/mempool.go
@@ -676,7 +676,7 @@ func (cache *mapTxCache) Push(tx types.Tx) bool {
 	// Use the tx hash in the cache
 	txHash := sha256.Sum256(tx)
 	if moved, exists := cache.map_[txHash]; exists {
-		cache.list.MoveToFront(moved)
+		cache.list.MoveToBack(moved)
 		return false
 	}