Merge pull request #1 from kir486680/Mult_Add_Tests

Creating a bunch of tests in Python instead of old tb's

.github/verilog_ci.yml → .github/workflows/verilog_ci.yml

@@ -12,9 +12,9 @@ jobs:
     - name: Setup Icarus Verilog
       run: sudo apt-get update && sudo apt-get install -y iverilog
 
+    - name: Install virtualenv
+      run: sudo apt-get install -y python3-virtualenv
+
     - name: Test Verilog Code
       run: |
         make test
-    
-    - name: Run Tests
-      run: vvp output_name.vvp

.gitignore

@@ -1,6 +1,9 @@
 *.vcd
 *.vvp
 *.DS_Store
+**/results.xml
+**/sim_build/
+**/build/
 
 # Byte-compiled / optimized / DLL files
 __pycache__/

src/block.v

@@ -17,8 +17,8 @@ module block(inp_north, inp_west, weight_in, outp_south, outp_east,  clk, rst, c
     );
     wire [31:0] add_result;
     fadd add_instance (
-        .a_operand(inp_north),
-        .b_operand(mul_result),
+        .a_in(inp_north),
+        .b_in(mul_result),
         .result(add_result)
     );
 

src/fadd.v

@@ -2,7 +2,7 @@
 
 
 module fadd(
-    input [`BIT_W-1:0] a_operand, b_operand, // Inputs in the format of IEEE-`EXP_W-154 Representation.
+    input [`BIT_W-1:0] a_in, b_in, // Inputs in the format of IEEE-`EXP_W-154 Representation.
     output [`BIT_W-1:0] result // Outputs in the format of IEEE-`EXP_W-154 Representation.
 );
 
@@ -20,38 +20,47 @@ wire [`EXP_W-1:0] exponent_b_add;
 wire [`M_W+1:0] significand_add;
 wire [`BIT_W-2:0] add_sum;
 
+wire [`EXP_W-1:0] exp_a, exp_b;
 
-//for operations always operand_a must not be less than b_operand
-assign {operand_a,operand_b} = (a_operand[`BIT_W-2:0] < b_operand[`BIT_W-2:0]) ? {b_operand,a_operand} : {a_operand,b_operand};
 
-assign exp_a = operand_a[`BIT_W-2:`M_W];
-assign exp_b = operand_b[`BIT_W-2:`M_W];
+//for operations always operand_a must not be less than b_in
+assign {operand_a,operand_b} = (a_in[`BIT_W-2:0] < b_in[`BIT_W-2:0]) ? {b_in,a_in} : {a_in,b_in};
+
+assign exp_a = operand_a[`BIT_W-2:`M_W]; // extract exponent from operand_a
+assign exp_b = operand_b[`BIT_W-2:`M_W]; // extract exponent from operand_b
 
 //Exception flag sets 1 if either one of the exponent is 255.
 assign Exception = (&operand_a[`BIT_W-2:`M_W]) | (&operand_b[`BIT_W-2:`M_W]);
 
-assign output_sign = operand_a[`BIT_W-1] ;
+assign output_sign = operand_a[`BIT_W-1] ; // since the operand_a is always greater than operand_b, the sign of the result will be same as operand_a.
 
+//operation_sub_addBar is 1 if we are doing subtraction else 0.
 assign operation_sub_addBar =  ~(operand_a[`BIT_W-1] ^ operand_b[`BIT_W-1]);
 
 //Assigining significand values according to Hidden Bit.
-assign significand_a = {1'b1,operand_a[`M_W-1:0]};
-assign significand_b = {1'b1,operand_b[`M_W-1:0]};
+assign significand_a = {1'b1,operand_a[`M_W-1:0]}; // expand the mantissa by 1 bit before multiplication since its always implied
+assign significand_b = {1'b1,operand_b[`M_W-1:0]}; // same as above
 
 //Evaluating Exponent Difference
 assign exponent_diff = operand_a[`BIT_W-2:`M_W] - operand_b[`BIT_W-2:`M_W];
 
-//Shifting significand_b according to exponent_diff
+//Shifting significand_b to the right according to exponent_diff. Exapmle: if we have 1.0101 >> 2 = 0.0101 then exponent_diff = 2 and significand_b_add = significand_b >> exponent_diff
 assign significand_b_add = significand_b >> exponent_diff;
 
+//Adding exponent_diff to exponent_b. Exapmle: if we have 1.0101 << 2 = 101.01 then exponent_diff = 2 and exponent_b_add = exponent_b + exponent_diff
 assign exponent_b_add = operand_b[`BIT_W-2:`M_W] + exponent_diff; 
 
 //------------------------------------------------ADD BLOCK------------------------------------------//
+//if we are adding(operation_sub_addBar=1) need to add significand_b_add to significand_a. 
+//Or sets the significand to zero if the signs are different(this means we are doing subtraction), effectively determining the core operation of the floating-point addition based on the sign of the operands.
 assign significand_add = ( operation_sub_addBar) ? (significand_a + significand_b_add) : {(`M_W+2){1'b0}}; 
 
-//Result will be equal to Most `M_W bits if carry generates else it will be Least `M_W-1 bits.
+//Taking care of the resulting mantissa. 
+//If there is a carry, then the result is normalized by shifting the significand right by one bit(because its implied) and incrementing the exponent by one.
+//If there is no carry, we just use the result of the addition, and we have `M_W-1:0 due to the fact that we are using the hidden bit(implied 1).
 assign add_sum[`M_W-1:0] = significand_add[`M_W+1] ? significand_add[`M_W:1] : significand_add[`M_W-1:0];
 
+// Taking care of the resulting exponent.
 //If carry generates in sum value then exponent must be added with 1 else feed as it is.
 assign add_sum[`BIT_W-2:`M_W] = significand_add[`M_W+1] ? (1'b1 + operand_a[`BIT_W-2:`M_W]) : operand_a[`BIT_W-2:`M_W];
 

src/fmul.v

@@ -17,7 +17,7 @@ module fmul(
 
     // Multiplication logic
     always @* begin
-        mul_fix_out = {1'b1, a_in[`M_W-1:0]} * {1'b1, b_in[`M_W-1:0]};
+        mul_fix_out = {1'b1, a_in[`M_W-1:0]} * {1'b1, b_in[`M_W-1:0]}; //extend the mantissa by 1 bit before multiplication
     end
 
     // Zero check
@@ -29,24 +29,34 @@ module fmul(
         end
     end
 
-    // Generate M
+    // Generate Mantissa. We are only considering the most significat bits of the product to generate the mantissa.
     always @* begin
+        //select two MSBs of the product
         case(mul_fix_out[`MULT_W-1:`MULT_W-2])
-            2'b01: M_result = mul_fix_out[`MULT_W-3:`M_W];
-            2'b10: M_result = mul_fix_out[`MULT_W-2:`M_W+1];
-            2'b11: M_result = mul_fix_out[`MULT_W-2:`M_W+1];
-            default: M_result = mul_fix_out[`MULT_W-2:`M_W+1];
+           //Example: If mul_fix_out is 8 bits wide and represents 01xxxxxx (binary), it extracts xxxxxx, assuming the MSBs are 01
+            2'b01: M_result = mul_fix_out[`MULT_W-3:`M_W]; //MSB is dropped(as it is always 1)
+            //In 2'b10 or 2'b11 case: 10yyyyyy → Shift → 0yyyyyy (Extract yyyyyy)
+            2'b10: M_result = mul_fix_out[`MULT_W-2:`M_W+1]; // Between two and just under 4. product larger than normalized range, so we need to shift right 
+            2'b11: M_result = mul_fix_out[`MULT_W-2:`M_W+1]; // same as line above. 
+            default: M_result = mul_fix_out[`MULT_W-2:`M_W+1]; // default same as two lines above
         endcase
     end
 
     // Overflow check
     always @* begin
+        //Different cases for overflow:
+        //1. If either of the inputs is zero, then the result is zero and there is no overflow.
+        //2. Underflow check: If the sum of the exponents is less than the minimum exponent, then the result is zero and there is no overflow. {2'b0,{(EXP_W-1){1'b1}}} is the minimum exponent(001111111 in case of 32bit float)
+        //3. Overflow check: If the sum of the exponents is greater than the maximum exponent, then the result is infinity and there is overflow. EXP_MAX is the maximum exponent.
         overflow = (zero_check || ({1'b0, a_in[`BIT_W-2:`M_W]} + {1'b0, b_in[`BIT_W-2:`M_W]} + {{`EXP_W{1'b0}}, mul_fix_out[`MULT_W-1]}) < {2'b0,{(`EXP_W-1){1'b1}}} || ({1'b0, a_in[`BIT_W-2:`M_W]} + {1'b0, b_in[`BIT_W-2:`M_W]} + {8'd0, mul_fix_out[`MULT_W-1]}) > `EXP_MAX);
 
         if (~zero_check) begin
             if (overflow) begin
                 e_result0 = {(`EXP_W+1){1'b1}};
             end else begin
+                //1. We extend the exponent by 1 bit because the result of addition of two exponents can be 1 bit larger than the exponent itself.
+                //2. We add the MSB of the mantissa multiplication(before normalization) to the exponent sum to account for the shifting of the mantissa.
+                //3. We subtract the bias from the exponent sum to get the final exponent because just adding two exponents would give us exp1 + exp2 + 2 x bias.
                 e_result0 = ({1'b0, a_in[`BIT_W-2:`M_W]} + {1'b0, b_in[`BIT_W-2:`M_W]} + {{`EXP_W{1'b0}}, mul_fix_out[`MULT_W-1]}) - {2'b0,{(`EXP_W-1){1'b1}}};
             end
         end else begin