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Two cycle of matrix mul work
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kir486680 committed Dec 22, 2023
1 parent 4ebde31 commit ee6d150
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Showing 4 changed files with 41 additions and 11 deletions.
12 changes: 11 additions & 1 deletion src/matrix_mul.v
Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,7 @@ always @(posedge clk or posedge rst) begin
end
end
GET_BLOCKS: begin

get_block_a <= 1;
get_block_b <= 1;
if (block_get_a_done && block_get_b_done) begin
Expand All @@ -163,12 +164,21 @@ always @(posedge clk or posedge rst) begin
ACCUMULATE: begin
add_block <= 1;
// Wait for the add operation to complete
//display matrix C and matrix res
for (int i = 0; i < `A_M*`B_N; i = i + 1) begin
$display("matrix_C[%d] = %d", i, matrix_C[i]);
$display("matrix_res[%d] = %d", i, matrix_res[i]);
end
if (block_add_done) begin
//the reason this is not a blocking statement is because somehow the next for loop which makes matrix_C = matrix_res would make matrix_C= matrix_res before add_block becomes 0,
//which would make matrix_res = 2 * matrix_C and not add the actual two matrices. However this might be fixed during actual synthesis.
add_block = 0;
//make matrix_C = matrix_res
for (int i = 0; i < `A_M*`B_N; i = i + 1) begin
matrix_C[i] <= matrix_res[i];
$display("matrix_C[%d] = %d", i, matrix_C[i]);
end
add_block <= 0;

// Update your loop counters here
r <= r + `K;
if (r >= `A_P) begin
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4 changes: 2 additions & 2 deletions tests/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@ VERILOG_SOURCES = ../src/define.v \
../src/matrix_mul.v

# You will have to create separate test rules for each module
#TOPLEVEL_LANG = verilog
TOPLEVEL_LANG = verilog
#TOPLEVEL = block_add
MODULE = test_block_add
#MODULE = test_block_add
TOPLEVEL = matrix_mul
MODULE = test_matrix_mul

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10 changes: 8 additions & 2 deletions tests/test_block_add.py
Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,18 @@ async def test_get_block(dut):
await RisingEdge(dut.clk)
for i in range(J*K):
dut.multiplied_block[i].value = BinaryValue(value=float_to_float16(i+1), n_bits=16)

dut.multiplied_block[0].value = BinaryValue(value=float_to_float16(113), n_bits=16)
dut.multiplied_block[1].value = BinaryValue(value=float_to_float16(62), n_bits=16)
dut.multiplied_block[2].value = BinaryValue(value=float_to_float16(35), n_bits=16)
dut.multiplied_block[3].value = BinaryValue(value=float_to_float16(20), n_bits=16)

# Initialize the buffer with sequential values
for i in range(buffer_size):
dut.buffer_temp[i].value = BinaryValue(value=float_to_float16(i), n_bits=16)

dut.buffer_temp[0].value = BinaryValue(value=float_to_float16(5), n_bits=16)
dut.buffer_temp[1].value = BinaryValue(value=float_to_float16(6), n_bits=16)
dut.buffer_temp[2].value = BinaryValue(value=float_to_float16(15), n_bits=16)
dut.buffer_temp[3].value = BinaryValue(value=float_to_float16(20), n_bits=16)
# Define the start row and column for the block to be read
start_row = 0
start_col = 0
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26 changes: 20 additions & 6 deletions tests/test_matrix_mul.py
Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,7 @@ async def test_get_block(dut):
print("Start of add", dut.block_add.start.value)
#print_matrix(dut.block_add.buffer_temp, J, K, "Input to block_add")
#print_matrix(dut.block_add.multiplied_block, J, K, "Input to block_add")
print_matrix(dut.block_add.buffer_result, 2,2, "Matrix C")
print("i,l,r", dut.i.value, dut.l.value, dut.r.value)
print_matrix(dut.block_add.buffer_result, 2,2, "Matrix C")
for i in range(8):
await RisingEdge(dut.clk)
print("Counter", dut.systolic_array.counter.value)
Expand All @@ -66,13 +65,16 @@ async def test_get_block(dut):
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
print_matrix(dut.block_add.multiplied_block, 2,2, "Multiplied Result")
print_matrix(dut.block_add.buffer_temp, 2,2, "Buffer Temp")
#print i and l
print(dut.add_block.value)
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
print_matrix(dut.matrix_res, J, K, "Resultant Matrix")

await RisingEdge(dut.clk)
print("Current state", dut.state.value)
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
await RisingEdge(dut.clk)
print("Current state", dut.state.value)

#here we should be going back to get block
print("-------------------------")
Expand All @@ -99,6 +101,18 @@ async def test_get_block(dut):
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
print("i,l,r", dut.i.value, dut.l.value, dut.r.value)
print("Next state", dut.next_state.value)
print("Next state", dut.next_state.value)
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
for i in range(8):
await RisingEdge(dut.clk)
print("Counter", dut.systolic_array.counter.value)
print_matrix(dut.mul_result, J, K, "Matrix a after mult")
print_matrix(dut.matrix_C, J, K, "matrix C")
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
await RisingEdge(dut.clk)
print("Current state", dut.state.value)
print_matrix(dut.matrix_C, J, K, "Resultant Matrix")


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