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drivers: versal: TRNG, PM, MBOX, NVM, ECC, RSA, HASH, AES-GCM
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When booting this OP-TEE, the tests get executed
This is the expected output.

OP-TEE build flags:
make -j 8 PLATFORM=versal \
         CFG_TEE_CORE_LOG_LEVEL=4 \
         CFG_VERSAL_TRACE_PLM=y \
         CFG_VERSAL_CRYPTO_DRIVER=y \
         CFG_CRYPTO_DRIVER_DEBUG=y \
         CFG_EARLY_TA=y \
         CFG_IN_TREE_EARLY_TAS=hello_world/8aaaf200-2450-11e4-abe2-0002a5d5c51b \
         -C /home/jramirez/Work/xilinx/project/local,optee-os \
         O=/home/jramirez/Work/xilinx/project/.build/op-tee

OP-TEE output:

I/TC: OP-TEE version: 3.16.0-184-gedfe0aa2-dev (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro
GCC 7.3-2018.05)) OP-TEE#1 vie 03 jun 2022 16:45:00 UTC aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
D/TC:0 0 call_preinitcalls:21 level 2 mobj_mapped_shm_init()
D/TC:0 0 mobj_mapped_shm_init:464 Shared memory address range: 60200000, 62200000
D/TC:0 0 call_initcalls:40 level 1 register_time_source()
D/TC:0 0 call_initcalls:40 level 1 versal_mbox_init()
D/TC:0 0 call_initcalls:40 level 1 teecore_init_pub_ram()
D/TC:0 0 call_initcalls:40 level 3 platform_banner()
I/TC: Platform Versal - Silicon Revision v2
D/TC:0 0 call_initcalls:40 level 3 check_ta_store()
D/TC:0 0 check_ta_store:408 TA store: "early TA"
D/TC:0 0 check_ta_store:408 TA store: "Secure Storage TA"
D/TC:0 0 check_ta_store:408 TA store: "REE"
D/TC:0 0 call_initcalls:40 level 3 early_ta_init()
D/TC:0 0 early_ta_init:57 Early TA 8aaaf200-2450-11e4-abe2-0002a5d5c51b size 23267 (compressed, uncompressed 38616)
D/TC:0 0 call_initcalls:40 level 3 verify_pseudo_tas_conformance()
D/TC:0 0 call_initcalls:40 level 3 tee_cryp_init()
D/TC:0 0 call_initcalls:40 level 4 tee_fs_init_key_manager()
D/TC:0 0 call_initcalls:40 level 5 trng_hrng_mode_init()
D/TC:0 0 call_initcalls:40 level 5 versal_nvm_test()
I/TC: Versal: Test NVM
I/TC: ---- wr usr fuse:                                  [OK]
I/TC: ---- rd usr fuse:                                  [OK]
I/TC: ---- rd dna fuse:                                  [OK]
I/TC: ---- rd ppk fuse:                                  [OK]
I/TC: ---- rd iv fuse:                                   [OK]
D/TC:0 0 call_initcalls:40 level 5 ecc_init()
D/TC:0 0 drvcrypt_register:16 Registering module id 6 with 0x0x6006f348
D/TC:0 0 call_initcalls:40 level 5 rsa_init()
D/TC:0 0 drvcrypt_register:16 Registering module id 3 with 0x0x6006f3d0
D/TC:0 0 call_initcalls:40 level 5 sha3_init()
D/TC:0 0 drvcrypt_register:16 Registering module id 0 with 0x0x600179bc
D/TC:0 0 call_initcalls:40 level 6 versal_crypto_test()
D/TC:0 0 drvcrypt_asym_alloc_ecc_keypair:353 ECC Keypair (1024 bits) alloc ret = 0x0
D/TC:0 0 ecc_generate_keypair:115 ECC Keypair (384 bits) generate ret = 0x0
D/TC:0 0 drvcrypt_asym_alloc_ecc_public_key:390 ECC Public Key (1024 bits) alloc ret = 0x0
D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid
D/TC:0 0 ecc_sign:187 Sign algo (0x70004041) returned 0x0
D/TC:0 0 algo_is_valid:60 Algo 0x70004041 curve 0x4 is valid
D/TC:0 0 ecc_verify:247 Verify algo (0x70004041) returned 0x0
I/TC: Versal: Test ECC
I/TC: ---- ecc gen pair:                                 [OK]
I/TC: ---- ecc gen sign:                                 [OK]
I/TC: ---- ecc ver sign:                                 [OK]
D/TC:0 0 call_initcalls:40 level 6 versal_register_authenc()
D/TC:0 0 drvcrypt_register:16 Registering module id 9 with 0x0x6006f460
D/TC:0 0 call_initcalls:40 level 6 mobj_init()
D/TC:0 0 call_initcalls:40 level 6 default_mobj_init()
D/TC:0 0 call_finalcalls:59 level 1 versal_crypto_test()
D/TC:0 0 crypto_acipher_alloc_rsa_keypair:36 RSA Keypair (4096 bits) alloc ret = 0x0
D/TC:0 0 crypto_acipher_rsanopad_decrypt:155 RSA Decrypt NO PAD ret = 0x0
D/TC:0 0 crypto_acipher_free_rsa_keypair:85 RSA Keypair free
D/TC:0 0 crypto_acipher_alloc_rsa_public_key:60 RSA Public Key (4096 bits) alloc ret = 0x0
D/TC:0 0 crypto_acipher_rsanopad_encrypt:214 RSA Encrypt NO PAD ret = 0x0
D/TC:0 0 crypto_acipher_free_rsa_public_key:72 RSA Public Key free
I/TC: Versal: Test RSA
I/TC: ---- rsa decrypt:                                  [OK]
I/TC: ---- rsa encrypt:                                  [OK]
D/TC:0 0 call_finalcalls:59 level 1 versal_sha3_test()
D/TC:0 0 drvcrypt_hash_alloc_ctx:18 hash alloc_ctx algo 0x50000005
D/TC:0 0 drvcrypt_hash_alloc_ctx:27 hash alloc_ctx ret 0x0
I/TC: Versal: Test HASH
I/TC: ---- hash sha384:                                  [OK]
D/TC:0 0 call_finalcalls:59 level 1 versal_authenc_test()
D/TC:0 0 drvcrypt_authenc_alloc_ctx:311 authenc alloc_ctx algo 0x40000810
D/TC:0 0 drvcrypt_authenc_alloc_ctx:330 authenc alloc_ctx ret 0x0
D/TC:0 0 authenc_init:107 authenc ret 0x0
D/TC:0 0 authenc_update_aad:139 authenc ret 0x0
D/TC:0 0 authenc_enc_final:231 authenc ret 0x0
D/TC:0 0 authenc_init:107 authenc ret 0x0
D/TC:0 0 authenc_update_aad:139 authenc ret 0x0
D/TC:0 0 authenc_dec_final:277 authenc ret 0x0
I/TC: Versal: Test AUTHENC
I/TC: ---- auth enc:                                     [OK]
I/TC: ---- auth dec:                                     [OK]
I/TC: Primary CPU switching to normal world boot
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x8000000
INFO:    SPSR = 0x3c9

U-Boot 2021.01-00106-gd8887ac90b (May 05 2022 - 10:00:18 +0200)

Signed-off-by: Jorge Ramirez-Ortiz <[email protected]>
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@ldts
ldts committed Jun 4, 2022
1 parent 3f957d1 commit 7a6a4ee
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Showing 25 changed files with 4,565 additions and 1 deletion.
16 changes: 16 additions & 0 deletions core/arch/arm/plat-versal/conf.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -32,3 +32,19 @@ $(call force,CFG_WITH_LPAE,y)
else
$(call force,CFG_ARM32_core,y)
endif

$(call force, CFG_VERSAL_RNG_DRV, y)
$(call force, CFG_WITH_SOFTWARE_PRNG,n)
$(call force, CFG_VERSAL_PM, y)
$(call force, CFG_VERSAL_MBOX, y)
$(call force, CFG_VERSAL_NVM, y)

# TRNG configuration
CFG_VERSAL_TRNG_SEED_LIFE ?= 3
CFG_VERSAL_TRNG_DF_MUL ?= 7

# MBOX configuration
CFG_VERSAL_MBOX_IPI_ID ?=3

# Crypto
CFG_VERSAL_CRYPTO_DRIVER ?= n
19 changes: 19 additions & 0 deletions core/arch/arm/plat-versal/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,8 @@
#include <console.h>
#include <drivers/gic.h>
#include <drivers/pl011.h>
#include <drivers/versal_nvm.h>
#include <drivers/versal_pm.h>
#include <kernel/boot.h>
#include <kernel/interrupt.h>
#include <kernel/misc.h>
Expand Down Expand Up @@ -56,3 +58,20 @@ void console_init(void)
CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
register_serial_console(&console_data.chip);
}

static TEE_Result platform_banner(void)
{
TEE_Result ret = TEE_SUCCESS;
uint8_t version = 0;

ret = versal_soc_version(&version);
if (ret) {
EMSG("Failure to retrieve SoC version");
return ret;
}

IMSG("Platform Versal - Silicon Revision v%d", version);

return TEE_SUCCESS;
}
service_init(platform_banner);
6 changes: 5 additions & 1 deletion core/arch/arm/plat-versal/platform_config.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,8 @@
#include <mm/generic_ram_layout.h>

/* Make stacks aligned to data cache line length */
#define STACK_ALIGNMENT 64
#define CACHELINE_LEN 64
#define STACK_ALIGNMENT CACHELINE_LEN

#if defined(PLATFORM_FLAVOR_generic)

Expand All @@ -29,6 +30,9 @@
#define DRAM0_BASE 0
#define DRAM0_SIZE 0x80000000

#define TRNG_BASE 0xF1230000
#define TRNG_SIZE 0x10000

#ifdef ARM64
/* DDR High area base is only available when compiling for 64 bits */
#define DRAM1_BASE 0x800000000
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2 changes: 2 additions & 0 deletions core/drivers/crypto/sub.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -9,3 +9,5 @@ subdirs-$(CFG_NXP_SE05X) += se050
subdirs-$(CFG_STM32_CRYPTO_DRIVER) += stm32

subdirs-$(CFG_ASPEED_CRYPTO_DRIVER) += aspeed

subdirs-$(CFG_VERSAL_CRYPTO_DRIVER) += versal
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