assert:read content of undefinedinsn address

read content of undefinedinsn address to catch possibly ram bit flip Signed-off-by: liaoao <[email protected]>
leo11261 · Nov 21, 2023 · d182b1a · d182b1a
1 parent eddd90d
commit d182b1a
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Showing 4 changed files with 40 additions and 4 deletions.
diff --git a/arch/arm/src/arm/arm_undefinedinsn.c b/arch/arm/src/arm/arm_undefinedinsn.c
@@ -42,7 +42,16 @@
 
 void arm_undefinedinsn(uint32_t *regs)
 {
-  _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+  if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 ":0x%" PRIx32 "\n",
+             regs[REG_PC], *(uint32_t *)regs[REG_PC]);
+    }
+  else
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+    }
+
   CURRENT_REGS = regs;
   PANIC_WITH_REGS("panic", regs);
 }
diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c
@@ -42,7 +42,16 @@
 
 uint32_t *arm_undefinedinsn(uint32_t *regs)
 {
-  _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+  if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 ":0x%" PRIx32 "\n",
+             regs[REG_PC], *(uint32_t *)regs[REG_PC]);
+    }
+  else
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+    }
+
   CURRENT_REGS = regs;
   PANIC_WITH_REGS("panic", regs);
   return regs; /* To keep the compiler happy */

diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c
@@ -42,7 +42,16 @@
 
 uint32_t *arm_undefinedinsn(uint32_t *regs)
 {
-  _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+  if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 ":0x%" PRIx32 "\n",
+             regs[REG_PC], *(uint32_t *)regs[REG_PC]);
+    }
+  else
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+    }
+
   CURRENT_REGS = regs;
   PANIC_WITH_REGS("panic", regs);
   return regs; /* To keep the compiler happy */

diff --git a/arch/arm/src/armv8-r/arm_undefinedinsn.c b/arch/arm/src/armv8-r/arm_undefinedinsn.c
@@ -42,7 +42,16 @@
 
 uint32_t *arm_undefinedinsn(uint32_t *regs)
 {
-  _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+  if (regs[REG_PC] >= (uint32_t)_stext && regs[REG_PC] < (uint32_t)_etext)
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 ":0x%" PRIx32 "\n",
+             regs[REG_PC], *(uint32_t *)regs[REG_PC]);
+    }
+  else
+    {
+      _alert("Undefined instruction at 0x%" PRIx32 "\n", regs[REG_PC]);
+    }
+
   CURRENT_REGS = regs;
   PANIC_WITH_REGS("panic", regs);
   return regs; /* To keep the compiler happy */