[MIPS] Expose FCSR

lifting-bits · Feb 23, 2024 · bbb3fa5 · bbb3fa5
1 parent 91e0d38
commit bbb3fa5
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diff --git a/include/remill/Arch/MIPS/Runtime/State.h b/include/remill/Arch/MIPS/Runtime/State.h
@@ -260,6 +260,11 @@ struct alignas(8) COP0Registers final {
   Reg DESAVE;
 } __attribute__((packed));
 
+struct alignas(8) COP1Registers final {
+  volatile uint64_t _0;
+  Reg FCSR;
+} __attribute__((packed));
+
 struct alignas(8) MIPSState : public ArchState {
   GPR gpr;  // 528 bytes.
 
@@ -276,6 +281,10 @@ struct alignas(8) MIPSState : public ArchState {
   COP0Registers cop0;
 
   uint64_t _3;
+
+  COP1Registers cop1;
+
+  uint64_t _4;
 } __attribute__((packed));
 
 struct State : public MIPSState {};

diff --git a/lib/Arch/Sleigh/MIPSArch.cpp b/lib/Arch/Sleigh/MIPSArch.cpp
@@ -309,6 +309,10 @@ class SleighMIPSArch : public ArchBase {
     REG(TAGHI, cop0.TagHi.qword, u64);
     REG(ERRORPC, cop0.ErrorEPC.qword, u64);
     REG(DESAVE, cop0.DESAVE.qword, u64);
+
+    // COP1
+    // TODO: Maybe move fpr here?
+    REG(FCSR, cop1.FCSR.dword, u32);
   }
 
   void