targets: manual define of the SDRAM PHY is no longer needed.

litex-hub · Apr 16, 2020 · 4185a01 · 4185a01
1 parent cb95962
commit 4185a01
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diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py
@@ -85,7 +85,6 @@ def __init__(self, toolchain="trellis", **kwargs):
                 platform.request("ddram"),
                 sys_clk_freq=sys_clk_freq)
             self.add_csr("ddrphy")
-            self.add_constant("ECP5DDRPHY")
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
@@ -67,7 +67,6 @@ def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
                 iodelay_clk_freq = 200e6,
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
@@ -66,7 +66,6 @@ def __init__(self, sys_clk_freq=int(125e6), **kwargs):
                 iodelay_clk_freq = 500e6,
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
@@ -116,7 +116,6 @@ def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
                 platform.request("ddram"),
                 sys_clk_freq=sys_clk_freq)
             self.add_csr("ddrphy")
-            self.add_constant("ECP5DDRPHY")
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py
@@ -94,7 +94,6 @@ def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=Fa
                 platform.request("ddram"),
                 sys_clk_freq=sys_clk_freq)
             self.add_csr("ddrphy")
-            self.add_constant("ECP5DDRPHY")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MT41J256M16(sys_clk_freq, "1:2"),

diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
@@ -66,7 +66,6 @@ def __init__(self, sys_clk_freq=int(125e6), **kwargs):
                 iodelay_clk_freq = 500e6,
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py
@@ -87,7 +87,6 @@ def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trell
                 platform.request("ddram"),
                 sys_clk_freq=sys_clk_freq)
             self.add_csr("ddrphy")
-            self.add_constant("ECP5DDRPHY")
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
@@ -65,7 +65,6 @@ def __init__(self, sys_clk_freq=int(125e6), **kwargs):
                 iodelay_clk_freq = 500e6,
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,