targets: rename usb_cdc to usb_acm.

As discussed recently on Discord.
litex-hub · Apr 30, 2020 · 78b5727 · 78b5727
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commit 78b5727
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diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py
@@ -26,7 +26,7 @@
 # - Place a 15K resistor between J4 pin 3 and J4 pin 4.
 # - Place a 1.5K resistor between J4 pin 1 and J4 pin 3.
 # - Connect USB DP (Green) to J4 pin 3, USB DN (White) to J4 pin 2.
-# ./colorlight_5a_75b.py --revision=7.0 --uart-name=usb_cdcc
+# ./colorlight_5a_75b.py --revision=7.0 --uart-name=usb_acm
 # ./colorlight_5a_75b.py --load
 # You should see the LiteX BIOS and be able to interact with it.
 #
@@ -102,7 +102,7 @@ def __init__(self, revision, with_ethernet=False, with_etherbone=False, sys_clk_
 
         # CRG --------------------------------------------------------------------------------------
         with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
-        with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
+        with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
         self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll=with_usb_pll,with_rst=with_rst)
 
         # SDR SDRAM --------------------------------------------------------------------------------

diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py
@@ -98,7 +98,7 @@ def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs):
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
+        with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
         self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
 
         # DDR3 SDRAM -------------------------------------------------------------------------------

diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py
@@ -73,7 +73,7 @@ def __init__(self, device="LFE5U-45F", toolchain="trellis",
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
+        with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
         self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
 
         # SDR SDRAM --------------------------------------------------------------------------------