targets/c10lprefkit: fix default sys-clk-freq.

litex-hub · Jan 12, 2021 · 9ff90eb · 9ff90eb
1 parent 0a7443d
commit 9ff90eb
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py
@@ -109,7 +109,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit")
     parser.add_argument("--build",         action="store_true", help="Build bitstream")
     parser.add_argument("--load",          action="store_true", help="Load bitstream")
-    parser.add_argument("--sys-clk-freq",  default=500e6,       help="System clock frequency (default: 50MHz)")
+    parser.add_argument("--sys-clk-freq",  default=50e6,       help="System clock frequency (default: 50MHz)")
     parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     builder_args(parser)
     soc_sdram_args(parser)