small fix

llvm · Oct 9, 2024 · 700af35 · 700af35
1 parent 4d83a5c
commit 700af35
Showing 1 changed file with 10 additions and 9 deletions.
diff --git a/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp b/lib/Conversion/SCFToCalyx/SCFToCalyx.cpp
@@ -1026,17 +1026,17 @@ LogicalResult BuildOpGroups::buildOp(PatternRewriter &rewriter,
   case CmpIPredicate::eq: {
     StringRef opName = op.getOperationName().split(".").second;
     Type width = op.getResult().getType();
-    auto condReg = createRegister(
-        op.getLoc(), rewriter, getComponent(), width.getIntOrFloatBitWidth(),
-        getState<ComponentLoweringState>().getUniqueName(opName));
-
-    for (auto *user : op->getUsers()) {
-      if (auto ifOp = dyn_cast<scf::IfOp>(user))
-        getState<ComponentLoweringState>().setCondReg(ifOp, condReg);
-    }
-
     bool isSequential = isPipeLibOp(op.getLhs()) || isPipeLibOp(op.getRhs());
     if (isSequential) {
+      auto condReg = createRegister(
+          op.getLoc(), rewriter, getComponent(), width.getIntOrFloatBitWidth(),
+          getState<ComponentLoweringState>().getUniqueName(opName));
+
+      for (auto *user : op->getUsers()) {
+        if (auto ifOp = dyn_cast<scf::IfOp>(user))
+          getState<ComponentLoweringState>().setCondReg(ifOp, condReg);
+      }
+
       calyx::RegisterOp pipeResReg;
       if (isPipeLibOp(op.getLhs()))
         pipeResReg = getState<ComponentLoweringState>().getPipeResReg(
@@ -1647,6 +1647,7 @@ class BuildControl : public calyx::FuncOpPartialLoweringPattern {
         FlatSymbolRefAttr symbolAttr = nullptr;
         auto condReg = getState<ComponentLoweringState>().getCondReg(ifOp);
         if (!condReg) {
+          llvm::errs() << "no condReg\n";
           auto condGroup = getState<ComponentLoweringState>()
                                .getEvaluatingGroup<calyx::CombGroupOp>(cond);