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[SimplifyCFG] Add tests for #89672 (NFC)
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@nikic
nikic committed Apr 23, 2024
1 parent 4127a69 commit 34ee77c
Showing 1 changed file with 64 additions and 16 deletions.
80 changes: 64 additions & 16 deletions llvm/test/Transforms/SimplifyCFG/speculate-store.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -120,14 +120,14 @@ define i32 @load_before_store_noescape(i64 %i, i32 %b) {
; CHECK-NEXT: [[A:%.*]] = alloca [2 x i32], align 8
; CHECK-NEXT: store i64 4294967296, ptr [[A]], align 8
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 [[I:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[B:%.*]]
; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[CMP]], i32 [[B]], i32 [[TMP1]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[B:%.*]]
; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[CMP]], i32 [[B]], i32 [[TMP0]]
; CHECK-NEXT: store i32 [[SPEC_STORE_SELECT]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 1
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i32 [[ADD]]
;
entry:
Expand Down Expand Up @@ -158,17 +158,17 @@ define i32 @load_before_store_escape(i64 %i, i32 %b) {
; CHECK-NEXT: store i64 4294967296, ptr [[A]], align 8
; CHECK-NEXT: call void @fork_some_threads(ptr [[A]])
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 [[I:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[B:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[B:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
; CHECK-NEXT: store i32 [[B]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 1
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: call void @join_some_threads()
; CHECK-NEXT: ret i32 [[ADD]]
;
Expand Down Expand Up @@ -205,18 +205,18 @@ define i32 @not_alone_in_block(i64 %i, i32 %b) {
; CHECK-NEXT: [[A:%.*]] = alloca [2 x i32], align 8
; CHECK-NEXT: store i64 4294967296, ptr [[A]], align 8
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 [[I:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP1]], [[B:%.*]]
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], [[B:%.*]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
; CHECK-NEXT: store i32 [[B]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: store i32 [[B]], ptr [[A]], align 4
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x i32], ptr [[A]], i64 0, i64 1
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP3]]
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i32 [[ADD]]
;
entry:
Expand All @@ -240,6 +240,54 @@ if.end:
ret i32 %add
}

; FIXME: This is a miscompile.
define void @wrong_align_store(ptr %A, i32 %B, i32 %C, i32 %D) {
; CHECK-LABEL: @wrong_align_store(
; CHECK-NEXT: entry:
; CHECK-NEXT: store i32 [[B:%.*]], ptr [[A:%.*]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 42
; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[CMP]], i32 [[C:%.*]], i32 [[B]]
; CHECK-NEXT: store i32 [[SPEC_STORE_SELECT]], ptr [[A]], align 8
; CHECK-NEXT: ret void
;
entry:
store i32 %B, ptr %A, align 4
%cmp = icmp sgt i32 %D, 42
br i1 %cmp, label %if.then, label %ret.end

if.then:
store i32 %C, ptr %A, align 8
br label %ret.end

ret.end:
ret void
}

; FIXME: This is a miscompile.
define void @wrong_align_load(i32 %C, i32 %D) {
; CHECK-LABEL: @wrong_align_load(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[D:%.*]], 42
; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = select i1 [[CMP]], i32 [[C:%.*]], i32 [[TMP0]]
; CHECK-NEXT: store i32 [[SPEC_STORE_SELECT]], ptr [[A]], align 8
; CHECK-NEXT: ret void
;
entry:
%A = alloca i32, align 4
load i32, ptr %A, align 4
%cmp = icmp sgt i32 %D, 42
br i1 %cmp, label %if.then, label %ret.end

if.then:
store i32 %C, ptr %A, align 8
br label %ret.end

ret.end:
ret void
}

; CHECK: !0 = !{!"branch_weights", i32 3, i32 5}
!0 = !{!"branch_weights", i32 3, i32 5}

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